Datasheet ADL5570 (Analog Devices) - 5

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ADL5570 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Y D 2 B N C T C C S G V N 4 3 2 1 PIN 1 VCC1 5 16 NC INDICATOR RFIN 6 15 RFOUT ADL5570 GND 7 14 RFOUT TOP VIEW VREG 8 13 NC (Not to Scale) 9 0 1 2 1 1 1 TL E C C F D N N O
2
C M
-00 29
NC = NO CONNECT
067 Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1, 11 to 13, 16 NC No Connect. Do not connect these pins. 2 VCC2 This power supply pin should be connected to the supply via a choke circuit (see Figure 10). 3, 7 GND Connected to Ground. 4 STBY When STBY is low (0 V), the device operates in transmit mode. When the radio is receiving data, STBY can be taken high (2.5 V), reducing supply current to 1 mA. 5 VCC1 Connect to Power Supply. 6 RFIN Matched RF Input. 8 VREG When VREG is low, the device goes into sleep mode, reducing supply current to 10 μA. When VREG is high (2.85 V), the device operates in its normal transmit mode. When high, VREG draws a bias current of approximately 10 mA. 9 CFLT A ground-referenced capacitor should be connected to this pin to reduce bias line noise (see Figure 10). 10 MODE Switches Between High Power and Low Power Modes. When MODE is low (0 V), the device operates in high power mode. When MODE is high (2.5 V), the device operates in low power mode. See Table 4 for appropriate biasing. In cases where the MODE feature is not used, this pin should be connected to ground through a 50 kΩ resistor. 14, 15 RFOUT Unmatched RF Output. These parallel outputs can be matched to 50 Ω using strip-line and shunt capacitance. The power supply voltage should be connected to these pins through a choke inductor. Exposed Paddle The exposed paddle should be soldered down to a low impedance ground plane (if multiple ground layers are present, use multiple vias (9 minimum) to stitch together the ground planes) for optimum electrical and thermal performance.
Table 4. VCC = 3.5 V Operating Modes1 Mnemonic High Power Mode, POUT > 10 dBm Low Power Mode, POUT ≤ 10 dBm Standby Mode Sleep Mode
VREG High High High Low MODE Low High X X STBY Low Low High X 1 X = don’t care.
Table 5. VREG, MODE, and STBY Pins Mnemonic Nominal High (V) High Range (V) Nominal Low (V) Low Range (V)
VREG 2.85 2.75 to 2.95 0 NA MODE 2.5 >2.4 0 <1 STBY 2.5 >2.4 0 <1 Rev. 0 | Page 5 of 12 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS VCC = 3.5 V ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS BASIC CONNECTIONS Power Supply RF Input Interface RF Output Interface Transmit/Standby Enable VREG Enable MODE High Power/Low Power Enable 64 QAM OFDMA PERFORMANCE POWER-ADDED EFFICIENCY EVALUATION BOARD MEASUREMENT SETUP USING THE ADL5570 EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE