Datasheet ADSP-SC582, ADSP-SC583, ADSP-SC584, ADSP-SC587, ADSP-SC589, ADSP-21583, ADSP-21584, ADSP-21587 (Analog Devices) - 8

link to page 11 link to page 11 link to page 7
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
The memory map in Table 4 gives the L1 memory address space and shows multiple L1 memory blocks offering a configurable
0x FFFF FFFF DMC1 (1GB)
mix of SRAM and cache.
0x C000 0000 DMC0 (1GB) 0x 8000 0000 L1 Master and Slave Ports SPI2 FLASH (512MB) 0x 6000 0000
Each SHARC+ core has two master and two slave ports to and
PCIe (256MB) 0x 5000 0000
from the system fabric. One master port fetches instructions.
SMC BANK 3 (64MB)
The second master port drives data to the system world. Both
0x 4C00 0000 SMC BANK 2 (64MB)
slave ports allow conflict free core/direct memory access (DMA)
0x 4800 0000 SMC BANK 1 (64MB)
streams to the individual memory blocks. For slave port
0x 4400 0000
addresses, refer to the L1 memory address map in Table 4.
SMC BANK 0 (64MB) 0x 4000 0000 SYSTEM MMR L1 On-Chip Memory Bandwidth 0x 3000 0000 RESERVED
The internal memory architecture allows programs to have four
0x 28F9 FFFF SHARC2 L1 MULTI-MEMORY SPACE
accesses at the same time to any of the four blocks, assuming no
0x 28A4 0000
block conflicts. The total bandwidth is realized using both the
RESERVED 0x 2879 FFFF
DMD and PMD buses.
SHARC1 L1 MULTI-MEMORY SPACE 0x 2824 0000 UNIFIED RESERVED BYTE ADDRESS Instruction and Data Cache 0x 202B FFFF SPACE L2 ROM 2 (2Mb)
The ADSP-SC58x/ADSP-2158x processors also include a
0x 2028 0000 RESERVED
traditional instruction cache (I-cache) and two data caches
0x 2020 7FFF L2 BOOT ROM 2 (0.25Mb)
(D-cache) (PM and DM caches). These caches support one
(SHARC Cores) 0x 2020 0000
instruction access and two data accesses over the DM and PM
RESERVED 0x 201B FFFF
buses, per CCLK cycle. The cache controllers automatically
L2 ROM 1 (2Mb)
manage the configured L1 memory. The system can configure
0x 2018 0000 RESERVED
part of the L1 memory for automatic management by the cache
0x 2010 7FFF L2 BOOT ROM 1 (0.25Mb)
controllers. The sizes of these caches are independently configu-
(SHARC Cores) 0x 2010 0000
rable from 0 kB to a maximum of 128 kB each. The memory not
RESERVED 0x 200B FFFF
managed by the cache controllers is directly addressable by the
L2 SRAM (2Mb)
processors. The controllers ensure the data coherence between
0x 2008 0000 RESERVED
the two data caches. The caches provide user-controllable fea-
0x 2000 7FFF L2 BOOT ROM 0 (0.25Mb)
tures such as full and partial locking, range-bound invalidation,
(ARM CORE 0) 0x 2000 0000 0x 2000 0000
and flushing.
RESERVED 0x 0039 FFFF L1 BLOCK 3 SRAM (1Mb) System Event Controller (SEC) Input 0x 0038 0000 RESERVED RESERVED ADDRESS SP SHARC PRIV
The output of the system event controller (SEC) controller is
0x 0031 FFFF E C A L1 BLOCK 2 SRAM (1Mb)
forwarded to the core event controller (CEC) to respond
0x 0030 0000 RESERVED
directly to all unmasked system-based interrupts. The SEC also
ARM 0x 002E FFFF A A C T E
supports nesting including various SEC interrupt channel arbi-
L1 BLOCK 1 SRAM (1.5Mb) E ADDRESS SP 0x 1000 1000 0x 002C 0000
tration options. For all SEC channels, the processor
ARM L2 CONFIG REGS (4KB) RESERVED 0x 1000 0000
automatically stacks the arithmetic status (ASTATx and
0x 0026 FFFF RESERVED L1 BLOCK 0 SRAM (1.5Mb)
ASTATy) registers and mode (MODE1) register in parallel with
0x 0000 7FFF 0x 0024 0000 RESERVED/CORE MMRs/ ARM BOOT (32KB)
the interrupt servicing.
OTHER MEMORY ALIASES 0x 0000 0000 0x 0000 0000 Core Memory-Mapped Registers (CMMR)
Figure 5. ADSP-SC58x/ADSP-2158x Memory Map The core memory-mapped registers control the L1 instruction and data cache, BTB, L2 cache, parity error, system control, The ADSP-SC58x/ADSP-2158x processors share architectural debug, and monitor functions. features with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-214xx, and ADSP-2116x SIMD SHARC processors,
SHARC+ CORE ARCHITECTURE
shown in Figure 4 and detailed in the following sections. The ADSP-SC58x/ADSP-2158x processors are code compatible
SIMD Computational Engine
at the assembly level with the ADSP-2148x, ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x, The SHARC+ core contains two computational processing ele- ADSP-2116x, and with the first-generation ADSP-2106x ments that operate as a single-instruction, multiple data (SIMD) SHARC processors. engine. Rev. B | Page 8 of 173 | December 2018 Document Outline System Features Memory Additional Features Table of Contents Revision History General Description ARM Cortex-A5 Processor Generic Interrupt Controller (GIC), PL390 (ADSP-SC58x Only) Generic Interrupt Controller Port0 (GICPORT0) Generic Interrupt Controller Port1 (GICPORT1) L2 Cache Controller, PL310 (ADSP-SC58x Only) SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers (USTAT) Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict-Cache Branch Target Buffer/Branch Predictor Addressing Spaces Additional Features System Infrastructure System L2 Memory SHARC+ Core L1 Memory in Multiprocessor Space One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant C ode (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Arm TrustZone Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Enhanced Parallel Peripheral Interface (EPPI) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Link Ports (LP) ADC Control Module (ACM) Interface 3-Phase Pulse Width Modulator (PWM) Units Ethernet Media Access Controller (EMAC) Audio Video Bridging (AVB) Support (10/100/1000 EMAC Only) Precision Time Protocol (PTP) IEEE 1588 Support Controller Area Network (CAN) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) PCI Express (PCIe) Housekeeping Analog-to-Digital Converter (HADC) USB 2.0 On the Go (OTG) Dual-Role Device Controller Media Local Bus (Media LB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts Mobile Storage Interface (MSI) System Acceleration FFT/IFFT Accelerator Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator Harmonic Analysis Engine (HAE) Sinus Cardinalis (SINC) Filter Digital Transmission Content Protection (DTCP) System Design Clock Management Reset Control Unit (RCU) Real-Time Clock (RTC) Clock Generation Unit (CGU) System Crystal Oscillator and USB Crystal Oscillator Clock Distribution Unit (CDU) Power-Up Clock Out/External Clock Booting Thermal Monitoring Unit (TMU) Power Supplies Power Management Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for the 349-Ball CSP_BGA Package 529-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for the 529-Ball CSP_BGA Package ADSP-SC58x/ADSP-2158x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Current from High Speed Peripheral Operation Data Transmission Current HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications TMU TMU Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing DDR3 SDRAM Clock and Control Cycle Timing DDR3 SDRAM Read Cycle Timing DDR3 SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface (EPPI) Timing Link Ports (LP) Serial Ports (SPORT) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port SPI Port—Master Timing SPI Port—Slave Timing SPI Port—SPI Ready (SPIx_RDY) Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose I/O Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing PWM — Medium Precision (MP) Mode Timing PWM — Heightened Precision (HP) Mode Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) PCI Express (PCIe) 10/100 EMAC Timing (ETH0 and ETH1) 10/100/1000 EMAC Timing (ETH0 Only) Sinus Cardinalis (SINC) Filter Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode Media LB (MLB) Mobile Storage Interface (MSI) Controller Timing Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 349-Ball CSP_BGA ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 529-Ball CSP_BGA Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide