Datasheet ADSP-SC582, ADSP-SC583, ADSP-SC584, ADSP-SC587, ADSP-SC589, ADSP-21583, ADSP-21584, ADSP-21587 (Analog Devices) - 9

link to page 12
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
The processing elements are referred to as PEx and PEy data
Context Switch
registers and each contain an arithmetic logic unit (ALU), mul- Many of the registers of the processor have secondary registers tiplier, shifter, and register file. PEx is always active and PEy is that can activate during interrupt servicing for a fast context enabled by setting the PEYEN mode bit in the mode control switch. The data, DAG, and multiplier result registers have sec- register (MODE1). ondary registers. The primary registers are active at reset, while Single instruction multiple data (SIMD) mode allows the pro- control bits in MODE1 activate the secondary registers. cessors to execute the same instruction in both processing elements, but each processing element operates on different
Universal Registers (USTAT)
data. This architecture efficiently executes math intensive DSP General-purpose tasks use the universal registers. The four algorithms. In addition to all the features of previous generation USTAT registers allow easy bit manipulations (set, clear, toggle, SHARC cores, the SHARC+ core also provides a new and sim- test, XOR) for all control and status peripheral registers. pler way to execute an instruction only on the PEy data register. The data bus exchange register (PX) permits data to pass SIMD mode also affects the way data transfers between memory between the 64-bit PM data bus and the 64-bit DM data bus or and processing elements because to sustain computational between the 40-bit register file and the PM or DM data bus. operation in the processing elements requires twice the data These registers contain hardware to handle the data width bandwidth. Therefore, entering SIMD mode doubles the band- difference. width between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values
Data Address Generators With Zero-Overhead Hardware
transfer with each memory or register file access.
Circular Buffer Support Independent, Parallel Computation Units
For indirect addressing and implementing circular data buffers in hardware, the ADSP-SC58x/ADSP-2158x processor uses the Within each processing element is a set of pipelined computa- two data address generators (DAGs). Circular buffers allow effi- tional units. The computational units consist of a multiplier, cient programming of delay lines and other data structures arithmetic/logic unit (ALU), and shifter. These units are required in digital signal processing, and are commonly used in arranged in parallel, maximizing computational throughput. digital filters and Fourier transforms. The two DAGs of the pro- These computational units support IEEE 32-bit single-precision cessors contain sufficient registers to allow the creation of up to floating-point, 40-bit extended-precision floating-point, IEEE 32 circular buffers (16 primary register sets and 16 secondary 64-bit double-precision floating-point, and 32-bit fixed-point sets). The DAGs automatically handle address pointer wrap- data formats. around, reduce overhead, increase performance, and simplify A multifunction instruction set supports parallel execution of implementation. Circular buffers can start and end at any mem- ALU and multiplier operations. In SIMD mode, the parallel ory location. ALU and multiplier operations occur in both processing ele-
Flexible Instruction Set Architecture (ISA)
ments per core. All processing operations take one cycle to complete. For all The ISA, a 48-bit instruction word, accommodates various par- floating-point operations, the processor takes two cycles to allel operations for concise programming. For example, the complete in case of data dependency. Double-precision float- processors can conditionally execute a multiply, an add, and a ing-point data take two to six cycles to complete. The processor subtract in both processing elements while branching and fetch- stalls for the appropriate number of cycles for an interlocked ing up to four 32-bit values from memory—all in a single pipeline plus data dependency check. instruction. Additionally, the double-precision floating-point instruction set is an addition to the SHARC+ core.
Core Timer Variable Instruction Set Architecture (VISA)
Each SHARC+ processor core also has a timer. This extra timer is clocked by the internal processor clock and is typically used as In addition to supporting the standard 48-bit instructions from a system tick clock for generating periodic operating system previous SHARC processors, the SHARC+ core processors sup- interrupts. port 16-bit and 32-bit opcodes for many instructions, formerly 48-bit in the ISA. This feature, called variable instruction set
Data Register File
architecture (VISA), drops redundant or unused bits within the 48-bit instruction to create more efficient and compact code. Each processing element contains a general-purpose data regis- The program sequencer supports fetching these 16-bit and 32- ter file. The register files transfer data between the computation bit instructions from both internal and external memories. units and the data buses, and store intermediate results. These VISA is not an operating mode; it is only address dependent 10-port, 32-register register files (16 primary, 16 secondary), (refer to memory map ISA/VISA address spaces in Table 7). combined with the enhanced Harvard architecture of the pro- Furthermore, it allows jumps between ISA and VISA instruc- cessor, allow unconstrained data flow between computation tion fetches. units and internal memory. The registers in the PEx data regis- ter file are referred to as R0–R15 and in the PEy data register file as S0–S15. Rev. B | Page 9 of 173 | December 2018 Document Outline System Features Memory Additional Features Table of Contents Revision History General Description ARM Cortex-A5 Processor Generic Interrupt Controller (GIC), PL390 (ADSP-SC58x Only) Generic Interrupt Controller Port0 (GICPORT0) Generic Interrupt Controller Port1 (GICPORT1) L2 Cache Controller, PL310 (ADSP-SC58x Only) SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers (USTAT) Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict-Cache Branch Target Buffer/Branch Predictor Addressing Spaces Additional Features System Infrastructure System L2 Memory SHARC+ Core L1 Memory in Multiprocessor Space One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant C ode (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Arm TrustZone Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Enhanced Parallel Peripheral Interface (EPPI) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Link Ports (LP) ADC Control Module (ACM) Interface 3-Phase Pulse Width Modulator (PWM) Units Ethernet Media Access Controller (EMAC) Audio Video Bridging (AVB) Support (10/100/1000 EMAC Only) Precision Time Protocol (PTP) IEEE 1588 Support Controller Area Network (CAN) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) PCI Express (PCIe) Housekeeping Analog-to-Digital Converter (HADC) USB 2.0 On the Go (OTG) Dual-Role Device Controller Media Local Bus (Media LB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts Mobile Storage Interface (MSI) System Acceleration FFT/IFFT Accelerator Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator Harmonic Analysis Engine (HAE) Sinus Cardinalis (SINC) Filter Digital Transmission Content Protection (DTCP) System Design Clock Management Reset Control Unit (RCU) Real-Time Clock (RTC) Clock Generation Unit (CGU) System Crystal Oscillator and USB Crystal Oscillator Clock Distribution Unit (CDU) Power-Up Clock Out/External Clock Booting Thermal Monitoring Unit (TMU) Power Supplies Power Management Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for the 349-Ball CSP_BGA Package 529-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for the 529-Ball CSP_BGA Package ADSP-SC58x/ADSP-2158x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Current from High Speed Peripheral Operation Data Transmission Current HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications TMU TMU Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing DDR3 SDRAM Clock and Control Cycle Timing DDR3 SDRAM Read Cycle Timing DDR3 SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface (EPPI) Timing Link Ports (LP) Serial Ports (SPORT) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port SPI Port—Master Timing SPI Port—Slave Timing SPI Port—SPI Ready (SPIx_RDY) Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose I/O Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing PWM — Medium Precision (MP) Mode Timing PWM — Heightened Precision (HP) Mode Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) PCI Express (PCIe) 10/100 EMAC Timing (ETH0 and ETH1) 10/100/1000 EMAC Timing (ETH0 Only) Sinus Cardinalis (SINC) Filter Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode Media LB (MLB) Mobile Storage Interface (MSI) Controller Timing Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 349-Ball CSP_BGA ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 529-Ball CSP_BGA Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide