Datasheet ADAU1777 (Analog Devices)

Four-ADC, Two-DAC, Low Power Codec with Audio Processor Data Sheet ADAU1777 FEATURES APPLICATIONS Programmable audio processing engine Noise canceling handsets, headsets, and headphones Fast (up to 768 kHz) and slow processing paths Bluetooth® active noise canceling (ANC) handsets, headsets, Biquad filters, limiters, volume controls, and mixing and headphones Low latency, 24-bit ADCs and DACs Personal navigation devices 102 dB SNR (through PGA and ADC with A weighted filter) Digital still and video cameras 108 dB combined SNR (through DAC and headphone with GENERAL DESCRIPTION A weighted filter) Serial port sampling rate from 8 kHz to 192 kHz
The ADAU1777 is a codec with four inputs and two outputs that
5 μs analog-to-analog latency
incorporates a digital processing engine to perform filtering,
4 single-ended analog inputs, configurable as microphone
level control, signal level monitoring, and mixing. The path
or line inputs
from the analog input to the DSP core to the analog output is
Dual stereo digital microphone inputs
optimized for low latency and is ideal for noise canceling headsets.
Stereo analog audio output, single-ended or differential,
With the addition of just a few passive components, a crystal,
configurable as either line output or headphone driver
and an EEPROM for booting, the ADAU1777 provides a complete
PLL supporting any input clock rate from 8 MHz to 27 MHz
headset solution.
Full duplex, asynchronous sample rate converters (ASRCs)
Note that throughout this data sheet, multifunction pins, such as
Power supplies
SCL/SCLK, are referred to either by the entire pin name or by a
Analog and digital input/output of 1.8 V to 3.3 V
single function of the pin, for example, SCLK, when only that
Digital signal processing (DSP) core of 1.1 V to 1.8 V
function is relevant.
Low power I2C and SPI control interfaces, self boot from I2C EEPROM 7 multipurpose (MPx) pins for digital controls and outputs FUNCTIONAL BLOCK DIAGRAM UT _O D DD G DD DD DD D PD DV RE AV AV AV IOV MICBIAS0 MICROPHONE BIAS GENERATORS POWER LDO MICBIAS1 ADAU1777 MANAGEMENT REGULATOR ADC_SDATA1/CLKOUT/MP6 AIN0 PGA CLOCK PLL ADC OSCILLATOR XTALI/MCLKIN XTALO HPOUTLP/LOUTLP AIN1 PGA DAC ADC HPOUTLN/LOUTLN INPUT/OUTPUT SIGNAL STEREO PDM DMIC0_1/MP4 DIGITAL ROUTING MODULATOR MICROPHONE DMIC2_3/MP5 INPUTS HPOUTRP/LOUTRP DAC HPOUTRN/LOUTRN AIN2 PGA DAC_SDATA/MP0 SERIAL ADC BIDIRECTIONAL INPUT/ ADC_SDATA0/PDMOUT/MP1 ASRCS OUTPUT BCLK/MP2 PORT DSP CORE: LRCLK/MP3 AIN3 PGA BIQUAD FILTERS, LIMITERS, I2C/SPI CONTROL ADC VOLUME CONTROLS, INTERFACE AND SELF BOOT MIXING CM S I ND ND ND ND S S LK SO OOT O C DG AG AG AG M /MI A LFB L/S
001
E C SD S ADDR0/ S ADDR1/
14796- Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT/OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS TYPICAL POWER MANAGEMENT SETTINGS DIGITAL FILTERS SPECIFICATIONS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP CLOCK INITIALIZATION PLL Bypass Setup PLL Enabled Setup Control Port Access During Initialization PLL Input Clock Divider Integer Mode Fractional Mode CLOCK OUTPUT POWER SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Signal Polarity Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias DIGITAL MICROPHONE INPUT ANALOG-TO-DIGITAL CONVERTERS (ADCs) ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Headphone Output Power-Up Sequencing Ground Centered Headphone Configuration Pop and Click Suppression Line Outputs DIGITAL-TO-ANALOG CONVERTERS (DACs) DAC Full-Scale Level Digital DAC Volume Control PDM OUTPUT ASYNCHRONOUS SAMPLE RATE CONVERTERS SIGNAL LEVELS SIGNAL PROCESSING INSTRUCTIONS DATA MEMORY PARAMETERS CONTROL PORT BURST MODE COMMUNICATION I2C PORT Addressing I2C Read and Write Operations SPI PORT Read/Write Subaddress Data Bytes SELF BOOT EEPROM Size Cyclic Redundancy Check (CRC) Delay Boot Time MULTIPURPOSE PINS PUSH-BUTTON VOLUME CONTROLS LIMITER COMPRESSION ENABLE PARAMETER BANK SWITCHING MUTE DSP BYPASS MODE SERIAL DATA INPUT/OUTPUT PORTS TRISTATING UNUSED CHANNELS APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING PCB STACKUP LOW LATENCY REGISTER SETTINGS REGISTER SUMMARY REGISTER DETAILS CLOCK CONTROL REGISTER PLL DENOMINATOR MSB REGISTER PLL DENOMINATOR LSB REGISTER PLL NUMERATOR MSB REGISTER PLL NUMERATOR LSB REGISTER PLL INTEGER SETTING REGISTER PLL LOCK FLAG REGISTER CLKOUT SETTING SELECTION REGISTER REGULATOR CONTROL REGISTER CORE CONTROL REGISTER SLEEP ON PROGRAM ADDRESS COUNT REGISTER FILTER ENGINE AND LIMITER CONTROL REGISTER DB VALUE REGISTER 0 READ DB VALUE REGISTER 1 READ DB VALUE REGISTER 2 READ CORE CHANNEL 0/CORE CHANNEL 1 INPUT SELECT REGISTER CORE CHANNEL 2/CORE CHANNEL 3 INPUT SELECT REGISTER DAC INPUT SELECT REGISTER PDM MODULATOR INPUT SELECT REGISTER SERIAL DATA OUTPUT 0/SERIAL DATA OUTPUT 1 INPUT SELECT REGISTER SERIAL DATA OUTPUT 2/SERIAL DATA OUTPUT 3 INPUT SELECT REGISTER SERIAL DATA OUTPUT 4/SERIAL DATA OUTPUT 5 INPUT SELECT REGISTER SERIAL DATA OUTPUT 6/SERIAL DATA OUTPUT 7 INPUT SELECT REGISTER ADC_SDATA0/ADC_SDATA1 CHANNEL SELECT REGISTER OUTPUT ASRC0/OUTPUT ASRC1 SOURCE REGISTER OUTPUT ASRC2/OUTPUT ASRC3 SOURCE REGISTER INPUT ASRC CHANNEL SELECT REGISTER ADC0/ADC1 CONTROL 0 REGISTER ADC2/ADC3 CONTROL 0 REGISTER ADC0/ADC1 CONTROL 1 REGISTER ADC2/ADC3 CONTROL 1 REGISTER ADC0 VOLUME CONTROL REGISTER ADC1 VOLUME CONTROL REGISTER ADC2 VOLUME CONTROL REGISTER ADC3 VOLUME CONTROL REGISTER PGA CONTROL 0 REGISTER PGA CONTROL 1 REGISTER PGA CONTROL 2 REGISTER PGA CONTROL 3 REGISTER PGA SLEW CONTROL REGISTER PGA 10 DB GAIN BOOST REGISTER INPUT AND OUTPUT CAPACITOR CHARGING REGISTER DSP BYPASS PATH REGISTER DSP BYPASS GAIN FOR PGA0 REGISTER DSP BYPASS GAIN FOR PGA1 REGISTER MICBIAS0_1 CONTROL REGISTER DAC CONTROL REGISTER DAC0 VOLUME CONTROL REGISTER DAC1 VOLUME CONTROL REGISTER HEADPHONE OUTPUT MUTES REGISTER SERIAL PORT CONTROL 0 REGISTER SERIAL PORT CONTROL 1 REGISTER TDM OUTPUT CHANNEL DISABLE REGISTER PDM ENABLE REGISTER PDM PATTERN SETTING REGISTER MP0 FUNCTION SETTING REGISTER MP1 FUNCTION SETTING REGISTER MP2 FUNCTION SETTING REGISTER MP3 FUNCTION SETTING REGISTER MP4 FUNCTION SETTING REGISTER MP5 FUNCTION SETTING REGISTER MP6 FUNCTION SETTING REGISTER PUSH-BUTTON VOLUME SETTINGS REGISTER PUSH-BUTTON VOLUME CONTROL ASSIGNMENT REGISTER DEBOUNCE MODES REGISTER HEADPHONE LINE OUTPUT SELECT REGISTER DECIMATOR POWER CONTROL REGISTER ASRC INTERPOLATOR AND DAC MODULATOR POWER CONTROL REGISTER ANALOG BIAS CONTROL 0 REGISTER ANALOG BIAS CONTROL 1 REGISTER DIGITAL PIN PULL-UP CONTROL 0 REGISTER DIGITAL PIN PULL-UP CONTROL 1 REGISTER DIGITAL PIN PULL-DOWN CONTROL 0 REGISTER DIGITAL PIN PULL-DOWN CONTROL 1 REGISTER DIGITAL PIN DRIVE STRENGTH CONTROL 0 REGISTER DIGITAL PIN DRIVE STRENGTH CONTROL 1 REGISTER FAST RATE CONTROL REGISTER DAC INTERPOLATION CONTROL REGISTER VOLUME CONTROL BYPASS REGISTER OUTLINE DIMENSIONS ORDERING GUIDE