link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 AD5116Data SheetABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any ParameterRating other conditions above those indicated in the operational VDD to GND –0.3 V to +7.0 V section of this specification is not implied. Exposure to absolute VA, VW , VB to GND GND − 0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect IA, IW , IB device reliability. Pulsed1 Frequency > 10 kHz THERMAL RESISTANCE RAW = 5 kΩ and 10 kΩ ±6 mA/d2 θJA is defined by JEDEC specification JESD-51, and the value is RAW = 80 kΩ ±1.5 mA/d2 dependent on the test board and test environment. Frequency ≤ 10 kHz R Table 5. Thermal Resistance AW = 5 kΩ and 10 kΩ ±6 mA/√d2 RAW = 80 kΩ ±1.5 mA/√d2 Package TypeθθUnitJAJC Continuous 8-Lead LFCSP 901 25 °C/W R AW = 5 kΩ and 10 kΩ ±6mA 1 R JEDEC 2S2P test board, still air (0 m/sec air flow). AW = 80 kΩ ±1.5mA Push Button Inputs −0.3 V to +7 V or V ESD CAUTION DD + 0.3 V (whichever is less) Operating Temperature Range3 −40°C to +125°C Maximum Junction Temperature (TJ Max) 150°C Storage Temperature Range −65°C to +150°C Reflow Soldering Peak Temperature 260°C Time At Peak Temperature 20 sec to 40 sec Package Power Dissipation (TJ max − TA)/θJA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Pulse duty factor. 3 Includes programming of EEPROM memory. Rev. B | Page 6 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Interface Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation RDAC Register Manual Increment Auto Scan Increment Low Wiper Resistance Feature EEPROM Automatic Save Enable Auto Save Manual Store End Scale Resistance Indicator RDAC Architecture Top Scale/Bottom Scale Architecture Programming the Variable Resistor Rheostat Operation—±8% Resistor Tolerance Programming the Potentiometer Divider Voltage Output Operation Terminal Voltage Operating Range Power-Up Sequence Layout and Power Supply Biasing Outline Dimensions Ordering Guide