Datasheet AD5116 (Analog Devices) - 10

AD5116 Data Sheet 0 0 V 5kΩ DD = 5V 5kΩ VDD = 5V V V A = 2.5V + 1VRMS 10kΩ 10kΩ –10 A = 2.5V + VIN V –10 V B = 2.5V 80kΩ 80kΩ B = 2.5V CODE = HALF SCALE fIN = 1kHz –20 NOISE FILTER = 22kHz –20 CODE = HALF SCALE NOISE FILTER = 22kHz –30 –30 B) –40 B) d d –40 N ( –50 N ( –50 HD + HD + –60 T T –60 –70 –70 –80 –80 –90 –100 –90 20 200 2k 20k 200k
020
0.001 0.01 0.1 1
023
FREQUENCY (Hz) AMPLITUDE (V rms)
09657- 09657- Figure 20. Total Harmonic Distortion + Noise (THD + N) vs. Frequency Figure 23. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude
80 0.35 5k + 250pF 80k + 150pF VDD = 5V 10k + 75pF 80k + 250pF V 70 A = VDD 10k + 150pF 5k + 0pF 0.30 V 10k + 250pF 5k + 75pF B = GND 80k + 0pF 5k + 150pF 0.25 5kΩ 60 80k + 75pF 10k + 0pF 10kΩ ) 80kΩ Hz E (V) 0.20 50 M G A H ( LT 0.15 40 IDT 0.10 IVE VO 30 T A BANDW L 0.05 RE 20 0 10 –0.05 0 –0.10 0 10 20 30 40 50 60
024 021
–1 1 3 5 7 9 CODE (Decimal) TIME (µs)
09657- 09657- Figure 21. Maximum Bandwidth vs. Code vs. Net Capacitance Figure 24. Maximum Transition Glitch
150 0.0025 1.2 Ω) TA = 25°C 5.5V ( 5V 3.3V 2.7V 1.0 ANCE 120 0.0020 T 2.3V Y IS S Y ILIT IT 0.8 B NS A N RE 90 0.0015 OB DE R O R Y E IT 0.6 P IP L E W 60 0.0010 TIV A AL BABI 0.4 UL NT RO E P M CUM 30 0.0005 0.2 INCRE 0 0 0 0 1 2 3 4 5 6
022
–600 –500 –400 –300 –200 –100 0 100 200 300 400 500 600
047
VDD (V)
09657-
RESISTOR DRIFT (ppm)
09657- Figure 22. Incremental Wiper on Resistance vs. VDD Figure 25. Resistor Lifetime Drift Rev. B | Page 10 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Interface Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation RDAC Register Manual Increment Auto Scan Increment Low Wiper Resistance Feature EEPROM Automatic Save Enable Auto Save Manual Store End Scale Resistance Indicator RDAC Architecture Top Scale/Bottom Scale Architecture Programming the Variable Resistor Rheostat Operation—±8% Resistor Tolerance Programming the Potentiometer Divider Voltage Output Operation Terminal Voltage Operating Range Power-Up Sequence Layout and Power Supply Biasing Outline Dimensions Ordering Guide