Datasheet AD4112 (Analog Devices) - 6

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AD4112 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
INTERNAL REFERENCE 100 nF external capacitor to AVSS Output Voltage REFOUT with respect to AVSS 2.5 V Initial Accuracy4, 7 REFOUT, TA = 25°C −0.12 +0.12 % of V Temperature Coefficient ±5 +12 ppm/°C Reference Load Current, ILOAD −10 +10 mA Power Supply Rejection AVDD (line regulation) 95 dB Load Regulation ∆VOUT/∆ILOAD 32 ppm/mA Voltage Noise eN, 0.1 Hz to 10 Hz, 2.5 V reference 4.5 μV rms Voltage Noise Density eN, 1 kHz, 2.5 V reference 215 nV/√Hz Turn On Settling Time 100 nF REFOUT capacitor 200 μs Short-Circuit Current, ISC 25 mA EXTERNAL REFERENCE INPUTS Differential Input Range VREF = (REF+) − (REF−) 1 2.5 AVDD V Absolute Voltage Limits Buffers Disabled AVSS −0.05 AVDD +0.05 V Buffers Enabled AVSS AVDD V REF± Input Current Buffers Disabled Input Current ±9 μA/V Input Current Drift External clock ±0.75 nA/V/°C Internal clock ±2 nA/V/°C Buffers Enabled Input Current ±100 nA Input Current Drift 0.25 nA/°C Normal Mode Rejection See the rejection parameter Common-Mode Rejection 95 dB TEMPERATURE SENSOR Accuracy After user calibration at 25°C ±2 °C Sensitivity 477 μV/K GENERAL-PURPOSE OUTPUTS With respect to AVSS (GPO0, GPO1) Floating State Output Capacitance 5 pF Output Voltage4 High, VOH Source current (ISOURCE) = 200 μA AVDD − 1 V Low, VOL Sink current (ISINK) = 800 μA AVSS + 0.4 V CLOCK Internal Clock Frequency 2 MHz Accuracy −2.5% +2.5% % Duty Cycle 50 % Output Voltage Low, VOL 0.4 V High, VOH 0.8 × IOVDD V Crystal Frequency 14 16 16.384 MHz Start-Up Time 10 μs External Clock (CLKIO) 2 2.048 MHz Duty Cycle 30 50 70 % Rev. 0 | Page 6 of 58 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION THEORY OF OPERATION POWER SUPPLIES Single-Supply Operation (AVSS = DGND) DIGITAL COMMUNICATION AD4112 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register CIRCUIT DESCRIPTION MULTIPLEXER CURRENT INPUTS VOLTAGE INPUTS Fully Differential Inputs Single-Ended Inputs Adjusting Voltage Input Gain AD4112 REFERENCE Internal Reference External Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE OUPUTS DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR ERRORB Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR APPLICATIONS INFORMATION GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE