Datasheet AD4112 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | Single Supply, 24-Bit, Sigma-Delta ADC with ±10 V and 0 mA to 20 mA Inputs |
| Seiten / Seite | 58 / 5 — Data Sheet. AD4112. SPECIFICATIONS. Table 1. Parameter. Test … |
| Revision | A |
| Dateiformat / Größe | PDF / 666 Kb |
| Dokumentensprache | Englisch |
Data Sheet. AD4112. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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Data Sheet AD4112 SPECIFICATIONS
AVDD = 3.0 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = 0 V, DGND = 0 V, VBIAS− = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock (MCLK) = 2 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
VOLTAGE INPUTS Differential Input Voltage Range1 Specified performance −10 +10 V Functional −VREF × 10 +VREF × 10 V Absolute (Pin) Input Voltage AVDD ≥ 4.75 V −20 +20 V AVDD = 3.0 V −12 +12 V Input Impedance 1 MΩ Offset Error2 25°C ±1.5 mV Offset Drift ±7 μV/°C Gain Error Internal full-scale calibration3, 25°C ±0.05 % of FS Gain Drift ±1 ppm/°C Integral Nonlinearity (INL) ±0.01 % of FSR Total Unadjusted Error (TUE)4 25°C, internal VREF ±0.06 % of FSR −40°C to +105°C, internal V REF ±0.1 % of FSR 25°C, external VREF ±0.06 % of FSR −40°C to +105°C, external V REF ±0.08 % of FSR Power Supply Rejection AVDD for VIN = 1 V 70 dB Common-Mode Rejection VIN = 1 V At DC 85 dB At 50 Hz, 60 Hz 20 Hz output data rate (postfilter), 50 Hz ± 120 dB 1 Hz and 60 Hz ± 1 Hz Normal Mode Rejection4 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB Resolution See Table 6 and Table 8 Noise See Table 6 and Table 8 CURRENT INPUTS Input Current Range −0.5 +24 mA Absolute (Pin) Input Voltage AVSS −0.05 AVDD +0.055 V Input Impedance6 54 60 75 Ω Offset Error2 ±2 μA Offset Drift ±3 nA/°C Gain Error Factory calibrated gain, 25°C ±0.02 % of FS Gain Drift ±10 ppm/°C INL ±0.01 % of FSR TUE4 25°C, internal VREF ±0.08 % of FSR −40°C to +105°C, internal VREF ±0.2 % of FSR 25°C, external VREF ±0.08 % of FSR −40°C to +105°C, external VREF ±0.2 % of FSR Power Supply Rejection AVDD for IIN = 10 mA 0.5 μA/V Normal Mode Rejection4 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB Resolution See Table 7 and Table 9 Noise See Table 7 and Table 9 ADC SPEED AND PERFORMANCE ADC Output Data Rate (ODR) One channel, see Table 6 1.25 31,250 SPS No Missing Codes4 Excluding sinc3 filter ≥ 15 kHz notch 24 Bits Rev. 0 | Page 5 of 58 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION THEORY OF OPERATION POWER SUPPLIES Single-Supply Operation (AVSS = DGND) DIGITAL COMMUNICATION AD4112 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register CIRCUIT DESCRIPTION MULTIPLEXER CURRENT INPUTS VOLTAGE INPUTS Fully Differential Inputs Single-Ended Inputs Adjusting Voltage Input Gain AD4112 REFERENCE Internal Reference External Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE OUPUTS DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR ERRORB Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR APPLICATIONS INFORMATION GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD4112 SPECIFICATIONS
AVDD = 3.0 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = 0 V, DGND = 0 V, VBIAS− = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock (MCLK) = 2 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
VOLTAGE INPUTS Differential Input Voltage Range1 Specified performance −10 +10 V Functional −VREF × 10 +VREF × 10 V Absolute (Pin) Input Voltage AVDD ≥ 4.75 V −20 +20 V AVDD = 3.0 V −12 +12 V Input Impedance 1 MΩ Offset Error2 25°C ±1.5 mV Offset Drift ±7 μV/°C Gain Error Internal full-scale calibration3, 25°C ±0.05 % of FS Gain Drift ±1 ppm/°C Integral Nonlinearity (INL) ±0.01 % of FSR Total Unadjusted Error (TUE)4 25°C, internal VREF ±0.06 % of FSR −40°C to +105°C, internal V REF ±0.1 % of FSR 25°C, external VREF ±0.06 % of FSR −40°C to +105°C, external V REF ±0.08 % of FSR Power Supply Rejection AVDD for VIN = 1 V 70 dB Common-Mode Rejection VIN = 1 V At DC 85 dB At 50 Hz, 60 Hz 20 Hz output data rate (postfilter), 50 Hz ± 120 dB 1 Hz and 60 Hz ± 1 Hz Normal Mode Rejection4 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB Resolution See Table 6 and Table 8 Noise See Table 6 and Table 8 CURRENT INPUTS Input Current Range −0.5 +24 mA Absolute (Pin) Input Voltage AVSS −0.05 AVDD +0.055 V Input Impedance6 54 60 75 Ω Offset Error2 ±2 μA Offset Drift ±3 nA/°C Gain Error Factory calibrated gain, 25°C ±0.02 % of FS Gain Drift ±10 ppm/°C INL ±0.01 % of FSR TUE4 25°C, internal VREF ±0.08 % of FSR −40°C to +105°C, internal VREF ±0.2 % of FSR 25°C, external VREF ±0.08 % of FSR −40°C to +105°C, external VREF ±0.2 % of FSR Power Supply Rejection AVDD for IIN = 10 mA 0.5 μA/V Normal Mode Rejection4 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB Resolution See Table 7 and Table 9 Noise See Table 7 and Table 9 ADC SPEED AND PERFORMANCE ADC Output Data Rate (ODR) One channel, see Table 6 1.25 31,250 SPS No Missing Codes4 Excluding sinc3 filter ≥ 15 kHz notch 24 Bits Rev. 0 | Page 5 of 58 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION THEORY OF OPERATION POWER SUPPLIES Single-Supply Operation (AVSS = DGND) DIGITAL COMMUNICATION AD4112 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register CIRCUIT DESCRIPTION MULTIPLEXER CURRENT INPUTS VOLTAGE INPUTS Fully Differential Inputs Single-Ended Inputs Adjusting Voltage Input Gain AD4112 REFERENCE Internal Reference External Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE OUPUTS DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR ERRORB Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR APPLICATIONS INFORMATION GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE