Datasheet ADSP-BF539, ADSP-BF539F (Analog Devices) - 9

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ADSP-BF539/ ADSP-BF539F
The DMA controllers support both 1-dimensional (1-D) and Like the other peripherals, the RTC can wake up the processor 2-dimensional (2-D) DMA transfers. DMA transfer initializa- from sleep mode upon generation of any RTC wake-up event. tion can be implemented from registers or from sets of Additionally, an RTC wake-up event can wake up the processor parameters called descriptor blocks. from deep sleep mode, and wake up the on-chip internal voltage The 2-D DMA capability supports arbitrary row and column regulator from a powered down state. sizes up to 64K elements by 64K elements and arbitrary row and Connect RTC pins RTXI and RTXO with external components column step sizes up to ±32K elements. Furthermore, the col- as shown in Figure 5. umn step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is
RTXI RTXO
especially useful in video applications where data can be deinterleaved on the fly.
R1
Examples of DMA types supported by the processor’s DMA controller include:
X1
• A single, linear buffer that stops upon completion
C1 C2
• A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer • 1-D or 2-D DMA using a linked list of descriptors
SUGGESTED COMPONENTS:
• 2-D DMA using an array o f descriptors, specifying only the
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
base DMA address within a common page
C1 = 22pF C2 = 22pF
In addition to the dedicated peripheral DMA channels, there are
R1 = 10M
: four memory DMA channels provided for transfers between the
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
various memories of the ADSP-BF539/ADSP-BF539F processor
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3pF.
system. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and Figure 5. External Components for RTC flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-
WATCHDOG TIMER
based methodology or by a standard register-based autobuffer The processors include a 32-bit timer that can be used to imple- mechanism. ment a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known
REAL-TIME CLOCK
state through generation of a hardware reset, nonmaskable The ADSP-BF539/ADSP-BF539F processor real-time clock interrupt (NMI), or general-purpose interrupt, if the timer (RTC) provides a robust set of digital watch features, including expires before being reset by software. Programs initialize the current time, stopwatch, and alarm. The RTC is clocked by a count value of the timer, enable the appropriate interrupt, and 32.768 kHz crystal external to the Blackfin processors. The RTC then enable the timer. Thereafter, the software must reload the peripheral has dedicated power supply pins so that it can remain counter before it counts to zero from the programmed value. powered up and clocked even when the rest of the processor is This protects the system from remaining in an unknown state in a low power state. The RTC provides several programmable where software, which would normally reset the timer, has interrupt options, including interrupt per second, minute, hour, stopped running due to an external noise condition or software or day clock ticks, interrupt on programmable stopwatch count- error. down, or interrupt at a programmed alarm time. If configured to generate a hardware reset, the watchdog timer The 32.768 kHz input clock frequency is divided down to a 1 Hz resets both the core and the processor peripherals. After a reset, signal by a prescaler. The counter function of the timer consists software can determine if the watchdog was the source of the of four counters: a 60-second counter, a 60-minute counter, a hardware reset by interrogating a status bit in the watchdog 24-hour counter, and an 32,768-day counter. timer control register. When enabled, the alarm function generates an interrupt when The timer is clocked by the system clock (SCLK), at a maximum the output of the timer matches the programmed value in the frequency of fSCLK. alarm control register. There are two alarms: the first alarm is for a time of day. The second alarm is for a day and time of
TIMERS
that day. There are four general-purpose programmable timer units in The stopwatch function counts down from a programmed the ADSP-BF539/ADSP-BF539F processors. Three timers have value, with one second resolution. When the stopwatch is an external pin that can be configured either as a pulse-width enabled and the counter underflows, an interrupt is generated. modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to Rev. F | Page 9 of 60 | October 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF539/ADSP-BF539F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF539F Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports Programmable I/O Pins Programmable Flags (GPIO Port F) General-Purpose I/O Ports C, D, and E Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Media Transceiver MAC layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Example Connections and Layout Considerations MXVR Board Layout Guidelines Voltage Regulator Layout Guidelines Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing MXVR Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide