Datasheet ADSP-BF539, ADSP-BF539F (Analog Devices) - 8

ADSP-BF539/ ADSP-BF539F
general-purpose interrupt to the IPEND output asserted is three
Table 3. System and Core Event Mapping (Continued)
core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.
Core Event Source Event Name Table 2. Core Event Controller (CEC)
DMA3 Interrupt (SPORT1 Rx) IVG9 DMA4 Interrupt (SPORT1 Tx) IVG9
Priority (0 is Highest) Event Class EVT Entry
DMA8 Interrupt (SPORT2 Rx) IVG9 0 Emulation/Test Control EMU DMA9 Interrupt (SPORT2 Tx) IVG9 1 Reset RST DMA10 Interrupt (SPORT3 Rx) IVG9 2 Nonmaskable Interrupt NMI DMA11 Interrupt (SPORT3 Tx) IVG9 3 Exception EVX DMA5 Interrupt (SPI0) IVG10 4 Reserved — DMA14 Interrupt (SPI1) IVG10 5 Hardware Error IVHW DMA15 Interrupt (SPI2) IVG10 6 Core Timer IVTMR DMA6 Interrupt (UART0 Rx) IVG10 7 General Interrupt 7 IVG7 DMA7 Interrupt (UART0 Tx) IVG10 8 General Interrupt 8 IVG8 DMA16 Interrupt (UART1 Rx) IVG10 9 General Interrupt 9 IVG9 DMA17 Interrupt (UART1 Tx) IVG10 10 General Interrupt 10 IVG10 DMA18 Interrupt (UART2 Rx) IVG10 11 General Interrupt 11 IVG11 DMA19 Interrupt (UART2 Tx) IVG10 12 General Interrupt 12 IVG12 Timer0, Timer1, Timer2 Interrupts IVG11 13 General Interrupt 13 IVG13 TWI0 Interrupt IVG11 14 General Interrupt 14 IVG14 TWI1 Interrupt IVG11 15 General Interrupt 15 IVG15 CAN Receive Interrupt IVG11 CAN Transmit Interrupt IVG11
Table 3. System and Core Event Mapping
MXVR Status Interrupt IVG11
Core
MXVR Control Message Interrupt IVG11
Event Source Event Name
MXVR Asynchronous Packet Interrupt IVG11 PLL Wake-Up Interrupt IVG7 Programmable Flags Interrupts IVG12 DMA Controller 0 Error IVG7 MDMA0 Stream 0 Interrupt IVG13 DMA Controller 1 Error IVG7 MDMA0 Stream 1 Interrupt IVG13 PPI Error Interrupt IVG7 MDMA1 Stream 0 Interrupt IVG13 SPORT0 Error Interrupt IVG7 MDMA1 Stream 1 Interrupt IVG13 SPORT1 Error Interrupt IVG7 Software Watchdog Timer IVG13 SPORT2 Error Interrupt IVG7
DMA CONTROLLERS
SPORT3 Error Interrupt IVG7 MXVR Synchronous Data Interrupt IVG7 The processors have multiple, independent DMA controllers that support automated data transfers with minimal overhead SPI0 Error Interrupt IVG7 for the processor core. DMA transfers can occur between the SPI1 Error Interrupt IVG7 ADSP-BF539/ADSP-BF539F processor internal memories and SPI2 Error Interrupt IVG7 any of its DMA capable peripherals. Additionally, DMA trans- UART0 Error Interrupt IVG7 fers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external UART1 Error Interrupt IVG7 memory interfaces, including the SDRAM controller and the UART2 Error Interrupt IVG7 asynchronous memory controller. DMA capable peripherals CAN Error Interrupt IVG7 include the SPORTs, SPI ports, UARTs, and PPI. Each individ- ual DMA capable peripheral has at least one dedicated DMA Real-Time Clock Interrupt IVG8 channel. In addition, the MXVR peripheral has its own dedi- DMA0 Interrupt (PPI) IVG8 cated DMA controller, which supports its own unique set of DMA1 Interrupt (SPORT0 Rx) IVG9 operating modes. DMA2 Interrupt (SPORT0 Tx) IVG9 Rev. F | Page 8 of 60 | October 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF539/ADSP-BF539F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF539F Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports Programmable I/O Pins Programmable Flags (GPIO Port F) General-Purpose I/O Ports C, D, and E Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Media Transceiver MAC layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Example Connections and Layout Considerations MXVR Board Layout Guidelines Voltage Regulator Layout Guidelines Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing MXVR Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide