Datasheet ADSP-BF606, ADSP-BF607, ADSP-BF608, ADSP-BF609 (Analog Devices) - 9

link to page 9 link to page 1 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Internal (Core-Accessible) Memory Booting
The L1 memory system is the highest-performance memory The processor has several mechanisms for automatically loading available to the Blackfin processor cores. internal and external memory after a reset. The boot mode is Each core has its own private L1 memory. The modified Har- defined by the SYS_BMODE input pins dedicated for this pur- vard architecture supports two concurrent 32-bit data accesses pose. There are two categories of boot modes. In master boot along with an instruction fetch at full processor speed which modes, the processor actively loads data from parallel or serial provides high bandwidth processor performance. In each core a memories. In slave boot modes, the processor receives data 64K-byte block of data memory partners with an 80K-byte from external host devices. memory block for instruction storage. Each data block is multi- The boot modes are shown in Table 2. These modes are imple- banked for efficient data exchange through DMA and can be mented by the SYS_BMODE bits of the reset configuration configured as SRAM. Alternatively, 16K bytes of each block can register and are sampled during power-on resets and software- be configured in L1 cache mode. The four-way set-associative initiated resets. instruction cache and the 2 two-way set-associative data caches greatly accelerate memory access performance, especially when
Table 2. Boot Modes
accessing external memories.
SYS_BMODE Setting Boot Mode
The L1 memory domain also features a 4K-byte scratchpad 000 No boot/Idle SRAM block which is ideal for storing local variables and the software stack. All L1 memory is protected by a multi-parity bit 001 Memory concept, regardless of whether the memory is operating in 010 RSI0 Master SRAM or cache mode. 011 SPI0 Master Outside of the L1 domain, L2 and L3 memories are arranged 100 SPI0 Slave using a Von Neumann topology. The L2 memory domain is a 101 Reserved unified instruction and data memory and can hold any mixture 110 LP0 Slave of code and data required by the system design. The L2 memory domain is accessible by both Blackfin cores through a dedicated 111 UART0 Slave 64-bit interface. It operates at SYSCLK frequency.
VIDEO SUBSYSTEM
The processor features up to 256K bytes of L2 SRAM which is ECC-protected and organized in eight banks. Individual banks The following sections describe the components of the proces- can be made private to any of the cores or the DMA subsystem. sor’s video subsystem. These blocks are shown with blue There is also a 32K-byte single-bank ROM in the L2 domain. It shading in Figure 1 on Page 1. contains boot code and safety functions.
Video Interconnect (VID) Static Memory Controller (SMC)
The Video Interconnect provides a connectivity matrix that The SMC can be programmed to control up to four banks of interconnects the Video Subsystem: three PPIs, the PIXC, and external memories or memory-mapped devices, with very flexi- the PVP. The interconnect uses a protocol to manage data ble timing parameters. Each bank occupies a 64M byte segment transfer among these video peripherals. regardless of the size of the device used, so that these banks are
Pipelined Vision Processor (PVP)
only contiguous if each is fully populated with 64M bytes of memory. The PVP engine provides hardware implementation of signal and image processing algorithms that are required for
Dynamic Memory Controller (DMC)
co-processing and pre-processing of monochrome video frames The DMC includes a controller that supports JESD79-2E com- in ADAS applications, robotic systems, and other machine patible double data rate (DDR2) SDRAM and JESD209A low applications. power DDR (LPDDR) SDRAM devices. The PVP works in conjunction with the Blackfin cores. It is
I/O Memory Space
optimized for convolution and wavelet based object detection and classification, and tracking and verification algorithms. The The processor does not define a separate I/O space. All PVP has the following processing blocks. resources are mapped through the flat 32-bit address space. On- • Four 5 × 5 16-bit convolution blocks optionally followed by chip I/O devices have their control registers mapped into mem- down scaling ory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller • A 16-bit cartesian-to-polar coordinate conversion block blocks, one which contains the control MMRs for all core func- • A pixel edge classifier that supports 1st and 2nd derivative tions, and the other which contains the registers needed for modes setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear • An arithmetic unit with 32-bit addition, multiply and as reserved space to on-chip peripherals. divide Rev. A | Page 9 of 112 | February 2014 Document Outline Blackfin Dual Core Embedded Processor Features Memory Table Of Contents Revision History General Description Blackfin Processor Core Instruction Set Description Processor Infrastructure DMA Controllers CRC Protection Event Handling Trigger Routing Unit (TRU) Pin Interrupts General-Purpose I/O (GPIO) Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Video Subsystem Video Interconnect (VID) Pipelined Vision Processor (PVP) Pixel Compositor (PIXC) Parallel Peripheral Interface (PPI) Processor Safety Features Dual Core Supervision Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Dual Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers 3-Phase PWM Units Link Ports Serial Ports (SPORTs) ACM Interface General-Purpose Counters Serial Peripheral Interface (SPI) Ports UART Ports TWI Controller Interface Removable Storage Interface (RSI) Controller Area Network (CAN) 10/100 Ethernet MAC USB 2.0 On-the-Go Dual-Role Device Controller Power and Clock Management Crystal Oscillator (SYS_XTAL) USB Crystal Oscillator Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit System Debug Unit Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF60x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GP I/O Multiplexing for 349-Ball CSP_BGA ADSP-BF60x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Processor — Absolute Maximum Ratings ESD Sensitivity Processor — Package Information Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read Asynchronous Flash Read Asynchronous Page Mode Read Synchronous Burst Flash Read Asynchronous Write Asynchronous Flash Write All Accesses Bus Request/Bus Grant DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface Timing Link Ports Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing General-Purpose Port Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing CAN Interface Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing RSI Controller Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions Thermal Diode ADSP-BF60x 349-Ball CSP_BGA Ball Assignments 349-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin Name) 349-Ball CSP_BGA Ball Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide