Datasheet LTC3541-1 (Analog Devices) - 8

HerstellerAnalog Devices
BeschreibungHigh Efficiency Buck + VLDO Regulator
Seiten / Seite22 / 8 — PIN FUNCTIONS VIN (Pin 1):. MODE (Pin 8):. ENBUCK (Pin 2):. BUCKFB (Pin …
Dateiformat / GrößePDF / 601 Kb
DokumentenspracheEnglisch

PIN FUNCTIONS VIN (Pin 1):. MODE (Pin 8):. ENBUCK (Pin 2):. BUCKFB (Pin 3):. ENVLDO (Pin 9):. LFB (Pin 4):. SW (Pin 10):

PIN FUNCTIONS VIN (Pin 1): MODE (Pin 8): ENBUCK (Pin 2): BUCKFB (Pin 3): ENVLDO (Pin 9): LFB (Pin 4): SW (Pin 10):

Modelllinie für dieses Datenblatt

Textversion des Dokuments

LTC3541-1
PIN FUNCTIONS VIN (Pin 1):
Main Supply Pin. This pin must be closely
MODE (Pin 8):
Buck Mode Selection Pin. This pin enables decoupled to GND with a 10µF or greater capacitor. buck Pulse-Skip operation when driven to a logic high
ENBUCK (Pin 2):
Buck Enable Pin. This pin enables the and enables buck Burst Mode operation when driven to buck regulator when driven to a logic high. a logic low.
BUCKFB (Pin 3):
Buck Regulator Feedback Pin. This pin
ENVLDO (Pin 9):
VLDO/Linear Regulator Enable Pin. When receives the buck regulator’s feedback voltage from an driven to a logic high, this pin enables the linear regulator external resistive divider. when the ENBUCK pin is driven to a logic low, and enables the VLDO when the ENBUCK pin is driven to a logic high.
LFB (Pin 4):
VLDO/Linear Regulator Feedback Pin. This pin receives either the VLDO or linear regulator’s feedback
SW (Pin 10):
Switch Node Pin. This pin connects the voltage from an external resistive divider. internal main and synchronous power MOSFET switches to the external inductor for the buck regulator.
LVOUT (Pin 5):
VLDO/Linear Regulator Output Pin. This pin provides the regulated output voltage from the VLDO
Exposed Pad (Pin 11):
Ground Pin. This pin must be or linear regulator. soldered to the PCB to provide both electrical contact to ground and good thermal contact to the PCB.
LVIN (Pin 6):
VLDO/Linear Regulator Input Supply Pin. This pin provides the input supply voltage for the VLDO
Note:
Table 1 details the truth table for the control pins power FET. of the LTC3541-1.
GND (Pin 7):
Analog Ground Pin.
Table 1. LTC3541-1 Control Pin Truth Table PIN NAME ENBUCK ENVLDO MODE OPERATIONAL DESCRIPTION
0 0 X LTC3541-1 Powered Down 0 1 X Buck Powered Down, VLDO Regulator Powered Down, Linear Regulator Enabled 1 0 0 Buck Enabled, VLDO Regulator Powered Down, Linear Regulator Powered Down, Burst Mode Operation 1 0 1 Buck Enabled, VLDO Regulator Powered Down, Linear Regulator Powered Down, Pulse-Skip Mode Operation 1 1 0 Buck Enabled, VLDO Regulator Enabled, Linear Regulator Powered Down, Burst Mode Operation 1 1 1 Buck Enabled, VLDO Regulator Enabled, Linear Regulator Powered Down, Pulse- Skip Mode Operation 35411fb 8 For more information www.linear.com/LTC3541-1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts