Datasheet LT1939 (Analog Devices) - 7

LT1939
PIN FUNCTIONS PG (Pin 4):
The power good pin is an open-collector
PG (Pin 7):
The power good bar pin is an open-collector output that sinks current when the FB or LFB falls below output that sinks current when the FB or LFB rises above 90% of its nominal regulating voltage. For VIN above 2V, 90% of its nominal regulating voltage. its output state remains true, although during SHDN, VIN
FB (Pin 8):
The FB pin is the negative input to the switcher undervoltage lockout, or thermal shutdown, its current error amplifi er. The output switches to regulate this pin to sink capability is reduced. 0.8V with respect to the exposed ground pad. Bias current
VC (Pin 5):
The VC pin is the output of the error amplifi er fl ows out of the FB pin. and the input to the peak switch current comparator. It is
LFB (Pin 9):
The LFB pin is the negative input to the linear normally used for frequency compensation, but can also error amplifi er. The L be used as a current clamp or control loop override. If DRV pin servo’s to regulate this pin to 0.8V with respect to the exposed ground pad. Bias current the error amplifi er drives VC above the maximum switch fl ows out of the LFB pin. current level, a voltage clamp activates. This indicates that the output is overloaded and current to be pulled from the
LDRV (Pin 10):
The LDRV pin is the emitter of an inter- SS pin reducing the regulation point. nal NPN that can be confi gured as an output of a linear regulator or as the drive for an external NPN high current
RT/SYNC (Pin 6):
This RT/SYNC pin provides two modes regulator. Current fl ows out of the LDRV pin when the of setting the constant switch frequency. LFB pin voltage is below 0.8V. The LDRV pin has a typical Connecting a resistor from the RT/SYNC pin to ground maximum current capability of 13mA. will set the RT/SYNC pin to a typical value of 1V. The
BST (Pin 11):
The BST pin provides a higher than V resultant switching frequency will be set by the resistor IN base drive to the power NPN to ensure a low switch drop. A value. The minimum value of 15kΩ and maximum value comparator to V of 200kΩ set the switching frequency to 2.5MHz and IN imposes a minimum off time on the SW pin if the BST pin voltage drops too low. Forcing a SW off 250kHz respectively. time allows the boost capacitor to recharge. Driving the RT/SYNC pin with an external clock signal
SW (Pin 12):
The SW pin is the emitter of the on-chip will synchronize the switch to the applied frequency. power NPN. At switch off, the inductor will drive this pin Synchronization occurs on the rising edge of the clock below ground with a high dV/dt. An external catch diode to signal after the clock signal is detected. Each rising clock ground, close to the SW pin and respective V edge initiates an oscillator ramp reset. A gain control loop IN decoupling capacitor’s ground, must be used to prevent this pin from servos the oscillator charging current to maintain a con- excessive negative voltages. stant oscillator amplitude. Hence, the slope compensation remains unchanged. If the clock signal is removed, the
Exposed Pad (Pin 13):
GND. The Exposed Pad is the oscillator reverts to resistor mode and reapplies the 1V only ground connection for the device. The Exposed Pad bias to the R should be soldered to a large copper area to reduce ther- T/SYNC pin after the synchronization detection circuitry times out. The clock source impedance should mal resistance. The GND pin also serves as small-signal be set such that the current out of the R ground. For ideal operation all small-signal ground paths T/SYNC pin in resistor mode generates a frequency roughly equivalent should connect to the GND pin at a single point, avoiding to the synchronization frequency. Floating or holding the any high current ground returns. RT/SYNC pin above 1.1V will not damage the device, but will halt oscillation. 1939f 7