Datasheet LT1939 (Analog Devices) - 9

LT1939
OPERATION
The LT1939 is a constant frequency, current mode buck the VC pin is driven low disabling switching and the soft- converter with an internal 2.3A switch plus a linear regula- start latch is reset. Once the latch is reset the soft-start tor with 13mA output capability. Control of both outputs capacitor starts to charge with a typical value of 2.75μA. is achieved with a common SHDN pin, internal regulator, As the voltage rises above 100mV on the SS pin, the V oscillator, undervoltage detect, soft-start, thermal shut- C pin will be driven high by the error amplifi er. When the down and power-on reset. voltage on the VC pin exceeds 0.8V, the clock set-pulse sets If the SHDN pin is taken below its 0.8V threshold, the the driver fl ip-fl op which turns on the internal power NPN LT1939 will be placed in a low quiescent current mode. switch. This causes current from VIN, through the NPN In this mode the LT1939 typically draws 12μA from the switch, inductor and internal sense resistor, to increase. VIN pin. When the voltage drop across the internal sense resistor When the SHDN pin is fl oated or driven above 0.76V, the exceeds a predetermined level set by the voltage on the internal bias circuits turn on generating an internal regu- VC pin, the fl ip-fl op is reset and the internal NPN switch lated voltage, 0.8(V is turned off. Once the switch is turned off the inductor FB) and 1V(RT/SYNC) references, and a POR signal which sets the soft-start latch. will drive the voltage at the SW pin low until the external Schottky diode starts to conduct, decreasing the current As the RT/SYNC pin reaches its 1V regulation point, the in the inductor. The cycle is repeated with the start of each internal oscillator will start generating a clock signal at a clock cycle. However, if the internal sense resistor voltage frequency determined by the resistor from the RT/SYNC exceeds the predetermined level at the start of a clock cycle, pin to ground. Alternatively, if a synchronization signal is the fl ip-fl op will not be set resulting in a further decrease in detected by the LT1939 at the RT/SYNC pin, a clock signal inductor current. Since the output current is controlled by will be generated at the incoming frequency on the rising the VC voltage, output regulation is achieved by the error edge of the synchronization pulse. In addition, the internal amplifi er continually adjusting the VC pin voltage. slope compensation will be automatically adjusted to pre- vent subharmonic oscillation during synchronization. The error amplifi er is a transconductance amplifi er that compares the FB voltage to either the SS pin voltage minus The LT1939 is a constant frequency, current mode step- 100mV or an internally regulated 800mV, whichever is down converter. Current mode regulators are controlled lowest. Compensation of the loop is easily achieved with by an internal clock and two feedback loops that control a simple capacitor or series resistor/capacitor from the the duty cycle of the power switch. In addition to the VC pin to ground. normal error amplifi er, there is a current sense amplifi er that monitors switch current on a cycle-by-cycle basis. Since the SS pin is driven by a constant current source, a This technique means that the error amplifi er commands single capacitor on the soft-start pin will generate controlled current to be delivered to the output rather than voltage. linear ramp on the output voltage. A voltage fed system will have low phase shift up to the If the current demanded by the output exceeds the maxi- resonant frequency of the inductor and output capacitor, mum current dictated by the VC pin clamp, the SS pin then an abrupt 180° shift will occur. The current fed system will be discharged, lowering the regulation point until the will have 90° phase shift at a much lower frequency, but output voltage can be supported by the maximum current. will not have the additional 90° shift until well beyond When overload is removed, the output will soft-start from the LC resonant frequency. This makes it much easier to the overload regulation point. frequency compensate the feedback loop and also gives VIN undervoltage detection or thermal shutdown will much quicker transient response. set the soft-start latch, resulting in a complete soft-start During power up, the POR signal sets the soft-start latch, sequence. which discharges the SS pin to ensure proper start-up The switch driver operates from either the VIN or BST volt- operation. When the SS pin voltage drops below 100mV, age. An external diode and capacitor are used to generate 1939f 9