Datasheet ADP5014 (Analog Devices) - 3

Data Sheet ADP5014 DETAILED FUNCTIONAL BLOCK DIAGRAM CHANNEL 1 – BUCK UVLO1 PVIN1 EN1/ENALL + EN_BUF 0.6V + – ACS1 – 1µA 3µA + HICCUP CLK1 PVIN1 MODE Q1 OCP – DRIVER SLOPE COMP + CMP1 SW1 – COMP1 PVIN1 Q2 E CONTROL LOGIC CH VSET1 + ARG AND MOSFET IT EA1 DRIVER WITH DRIVER SCH SW – CLK1 ANTICROSS DI PROTECTION PGND1 FREQ ZERO FB1 FOLDBACK CROSS OVP LATCH-UP – + NEG CURRENT CMP 0.9 VID1 1.15 + – PWRGD1 CURRENT BALANCE EN2/DL12 CHANNEL 2 – BUCK PVIN2 COMP2 DUPLICATE CHANNEL 1 SW2 VSET2 FB2 PGND2 RT OSCILLATOR CLK CFG1 FUNCTION HOUSE-KEEPING DECODER REF VREF LOGIC CFG2 GPIO UVLO AVIN CHANNEL 3 – BUCK UVLO3 PVIN3 EN3/UV + EN_BUF 0.6V + – ACS3 – 1µA 3µA + HICCUP CLK3 PVIN3 MODE Q5 OCP – DRIVER SLOPE COMP + CMP3 SW3 – COMP3 PVIN3 Q6 E RG CH VSET3 + CONTROL LOGIC IT EA3 AND MOSFET DRIVER SCHA SW – CLK3 DRIVER WITH DI ANTICROSS PROTECTION PGND3 FREQ ZERO FB3 FOLDBACK CROSS OVP – LATCH-UP + NEG CURRENT CMP 0.9 VID3 1.15 + – PWRGD3 CURRENT BALANCE EN4/DL34 PVIN4 CHANNEL 4 – BUCK COMP4 DUPLICATE SW4 CHANNEL 3 VSET4
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FB4 PGND4
00 6- 549 1 Figure 2. Rev. 0 | Page 3 of 34 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode FPWM and Automatic PWM/PSM Modes LOW NOISE ARCHITECTURE INTERNAL REFERENCE (VREF) ADJUSTABLE OUTPUT VOLTAGE FUNCTION CONFIGURATIONS (CFG1 AND CFG2) PARALLEL OPERATION MANUAL/SEQUENCE MODE Manual Mode (Precision Enable) Sequence Mode GENERAL PURPOSE INPUT/OUTPUT (GPIO) OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT POWER-GOOD FUNCTION UV COMPARATOR (SEQUENCE MODE ONLY) SOFT START STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLD BACK SHORT-CIRCUIT PROTECTION (SCP) OVERVOLTAGE PROTECTION UNDERVOLTAGE LOCKOUT ACTIVE OUTPUT DISCHARGE SWITCH THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CONFIGUATIONS (CFG1 AND CFG2) SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR DESIGNING THE COMPENSATION NETWORK PCB LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE