Datasheet LT6554 (Analog Devices) - 8

LT6554
U U W U APPLICATIO S I FOR ATIO Power Supplies Input Considerations
The LT6554 is optimized for ±5V supplies but can be The LT6554 input voltage range is from V– + 1V to V+ – 1V operated on as little as ±2.25V or a single 4.5V supply and and is therefore larger than the output swing. The inputs as much as ±6V or a single 12V supply. Internally, each can be driven beyond the point at which the output clips so supply is independent to improve channel isolation.
Do
long as input currents are limited to below ±10mA.
not leave any supply pins disconnected! Layout and Grounding Enable/Shutdown
It is imperative that care is taken in PCB layout in order to The LT6554 has a TTL compatible shutdown mode con- utilize the very high speed and very low crosstalk of the trolled by the EN pin and referenced to the DGND pin. If the LT6554. Separate power and ground planes are highly amplifier will be enabled at all times, the EN pin can be recommended and trace lengths should be kept as short connected directly to DGND. If the enable function is as possible. If input traces must be run over a distance of desired, either driving the pin above 2V or allowing the several centimeters, they should use a controlled imped- internal 46k pull-up resistor to pull the EN pin to the top rail ance with either series or shunt terminations (nominally will disable the amplifier. When disabled, the output will 50Ω or 75Ω) to maintain signal fidelity. become very high impedance. Supply current into the Care should be taken to minimize capacitance on the amplifier in the disabled state will be primarily through V+ LT6554’s output traces by increasing spacing between and approximately equal to (V+ – VEN)/46k. traces and adjacent metal and by eliminating metal planes It is important that the two following constraints on the in underlying layers. To drive cable or traces longer than DGND pin and the EN pin are always followed: several centimeters, using the LT6553 with its fixed gain
V+ – V
of +2 in conjunction with series and load termination
DGND
≥
3V V
resistors may provide better results.
EN – VDGND
≤
5.5V
Split supplies of ±3V to ±5.5V will satisfy these require- A plot of LT6554 performance driving a 1k load with ments with DGND connected to 0V. various trace lengths is shown in Figure 1. All data is from a 4-layer board with 2oz copper, 18mil of board layer In single supply applications above 5.5V, an additional thickness to the ground plane, a trace width of 12mils and resistor may be needed from the EN pin to DGND if the pin spacing to adjacent metal of 18mils. The 0.2cm output is ever allowed to float. For example, on a 12V single trace places the 1k resistor as close to the part as possible, supply, a 33k resistor to ground would protect the pin from while the other curves show the load resistor consecu- floating too high while still allowing the internal pull-up tively further away. The worst case, 4cm, trace has almost resistor to disable the part. 10pF of parasitic capacitance. On dual ±2.25V supplies, connecting the EN and DGND In order to counteract any peaking in the frequency re- pins to V– is the easiest way of ensuring that V+ – VDGND sponse from driving a capacitive load, a series resistance is more than 3V. can be inserted in the line at the output of the part to flatten The DGND pin should not be pulled above the EN pin since the response. Figure 2 shows the frequency response with doing so will turn on an ESD protection diode. If the EN pin the same 4cm trace from Figure 1, now with a 10Ω series voltage is forced a diode drop below the DGND pin, current resistor inserted near the output pin of the LT6554. Note should be limited to 10mA or less. that using a 10Ω series resistor with a 1k load only The enable/disable times of the LT6554 are fast when decreases the output amplitude by 0.1dB or 1% and has a driven with a logic input. Turn on (from 50% EN input to minimal effect on the bandwidth of the system. See the 50% output) typically occurs in less than 50ns. Turn off is graph labeled “Maximum Capacitive Load vs Output Se- slower, but is nonetheless below 300ns. ries Resistor” in the Typical Performance Characteristics section for more information. 6554fa 8