Datasheet LT6554 (Analog Devices) - 9

LT6554
U U W U APPLICATIO S I FOR ATIO
6 supply. The smallest value capacitors should be placed VS = ±5V VOUT = 200mVP-P closest to the package. 4 RL = 1k 4cm TRACE TA = 25°C To maintain the LT6554’s channel isolation, it is beneficial 2 to shield parallel input and output traces using a ground 2cm TRACE plane or power supply traces. Vias between topside and 0 0.2cm TRACE backside metal are recommended to maintain a low AMPLITUDE (dB) –2 inductance ground, especially between closely spaced signal traces. –4
Single Supply Operation
–60.1 1 10 100 1000 FREQUENCY (MHz) Figure 3 illustrates how to use the LT6554 with a single 6554 F01 supply ranging from 4.5V to 12V. Since the output range
Figure 1. Response vs Output Trace Length
is comparable to the input range, the DC bias point at the input can be set anywhere between the supplies that will 6 prevent the AC-coupled signal from running into the VS = ±5V V output range limits. As shown, the DC input level is mid- OUT = 200mVP-P 4 RL = 1k 4cm TRACE supply. TA = 25°C 2 The only additional power dissipation in the single supply configuration is through the resistor bias string at the 0 4cm TRACE input and through any load resistance at the output. In RS, OUT = 10Ω AMPLITUDE (dB) –2 many cases, the output can be used to directly drive other single supply devices without additional coupling and –4 without any resistive load. –60.1 1 10 100 1000
ESD Protection
FREQUENCY (MHz) 6554 F02 The LT6554 has reverse-biased ESD protection diodes on all pins. If any pins are forced a diode drop above the
Figure 2. Response vs Series Output Resistance
positive supply or a diode drop below the negative supply, While the AGND pins on the LT6554 are not connected to large currents may flow through these diodes. If the the amplifier circuitry, tying them to ground or another current is kept below 10mA, no damage to the device will “quiet” node significantly increases channel isolation and occur. is always recommended. The AGND pins do have ESD protection and therefore should not be connected to 4.5V TO 12V potentials outside the power supply range. Low ESL/ESR bypass capacitors should be placed as close 5k 22µF to the positive and negative supply pins as possible. One IN V+ VIN 4700pF ceramic capacitor is recommended for both V+ 1/3 OUT LT6554 and V–. Additional 470pF ceramic capacitors with minimal AGND 5k V– trace length on each supply pin will further improve AC and transient response as well as channel isolation. For high 6554 F03 current drive and large-signal transient applications, addi- tional 1µF to 10µF tantalums should be added on each
Figure 3. Single Supply Configuration, One Channel Shown
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