Datasheet LT3992 (Analog Devices) - 8

HerstellerAnalog Devices
BeschreibungMonolithic Dual Tracking 3A Step-Down Switching Regulator
Seiten / Seite36 / 8 — pin FuncTions. BST1/2:. ILIM1/2:. CMPI1/2:. IND1/2:. CMPO1/2:. RT/SYNC:. …
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DokumentenspracheEnglisch

pin FuncTions. BST1/2:. ILIM1/2:. CMPI1/2:. IND1/2:. CMPO1/2:. RT/SYNC:. DIV:. DNC:. GND:. only ground connec-. tion. FB1/2:

pin FuncTions BST1/2: ILIM1/2: CMPI1/2: IND1/2: CMPO1/2: RT/SYNC: DIV: DNC: GND: only ground connec- tion FB1/2:

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LT3992
pin FuncTions BST1/2:
The BST pin provides a higher than VIN base
ILIM1/2:
The voltage present at the ILIM pin determines drive to the power NPN to ensure a low switch drop. If the the peak inductor current for the channel. The ILIM pin is voltage between the BST pin and the VIN pin is less than driven by an internal current source with a typical value the voltage required to fully turn on the power NPN, the of 12µA. A resistor from the ILIM pin to ground sets the power switch is turned off to recharge the BST capacitor. ILIM voltage; the resistor value must be between 42.2k
CMPI1/2:
The CMPI pin is an input to a comparator with a and 120k. The maximum current limit range is 4.8A to threshold of 725mV and 80mV of hysteresis. Connecting 1.8A when the ILIM voltages are 1V and 0.5V respectively. the CMPI pin to the FB pin will generate a power good
IND1/2:
The IND pin is the input to the internal sense resistor signal when the output is within 90% of its regulated value. that measures current flowing in the inductor. When the
CMPO1/2:
The CMPO pin is an open-collector output that current in the resistor exceeds the current dictated by the sinks current when the CMPI pin falls below its threshold. VC pin, the SW latch is held in reset, disabling the output For a typical input voltage above 2.9V, its output state re- switch. Bias current flows out of the IND pin. mains true, although during shutdown, VIN1 undervoltage
RT/SYNC:
The voltage present at the RT/SYNC pin deter- lockout or thermal shutdown, its current sink capability is mines the constant switching frequency. The RT/SYNC reduced. The COMPO pins can be left open circuit or tied pin is driven by an internal current source with a typical together to form a single power good signal. value of 12µA which allows a single resistor from the RT/
DIV:
The voltage present at the DIV pin determines the ratio SYNC pin to ground to set the RT/SYNC voltage and result- of channel 1 frequency to the master clock frequency set ing switching frequency. Minimum switching frequency by the RT/SYNC pin. The DIV pin is driven by an internal is typically 110kHz when VRT/SYNC is 0V and maximum current source with a typical value of 12µA which allows switching frequency is typically 2.5MHz when VRT/SYNC a single resistor from the DIV pin to ground to set the is above 950mV. DIV voltage and resulting channel 1 frequency divider. Driving the RT/SYNC pin with an external clock signal will Ratios of 1, 2, 4 and 8 are available. See the Applications synchronize the switch to the applied frequency. Synchro- Information section for more information. nization occurs on the rising edge of the clock signal after
DNC:
Do Not Connect. the clock signal is detected. Each rising clock edge initiates an oscillator ramp reset. A gain control loop servos the
GND:
The exposed pad pin is the
only ground connec-
oscillator charging current to maintain constant oscillator
tion
for the device. The exposed pad should be soldered amplitude. Hence, the slope compensation and channel to a large copper area to reduce thermal resistance. The phase relationship remain unchanged. If the clock signal GND pin is common to both channels and also serves as is removed, the oscillator reverts to resistor mode after small-signal ground. For ideal operation all small-signal the synchronization detection circuitry times out. The clock ground paths should connect to the GND pin at a single source impedance should be set such that the current out point avoiding any high current ground returns. of the RT/SYNC pin in resistor mode generates a frequency
FB1/2:
The FB pin is the negative input to the error amplifier. roughly equivalent to the synchronization frequency. See The output switches to regulate this pin to 806mV with the Applications Information section for more information. respect to the exposed ground pad. Bias current flows out of the FB pin. 3992fa 8 For more information www.linear.com/LT3992 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts