Datasheet LT3992 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | Monolithic Dual Tracking 3A Step-Down Switching Regulator |
| Seiten / Seite | 36 / 9 — pin FuncTions SHDN1/2:. TJ:. C1/2:. SS1/2:. IN1:. VIN2:. VOUT1/2:. … |
| Dateiformat / Größe | PDF / 678 Kb |
| Dokumentensprache | Englisch |
pin FuncTions SHDN1/2:. TJ:. C1/2:. SS1/2:. IN1:. VIN2:. VOUT1/2:. CLKOUT:. SW1/2:
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Textversion des Dokuments
LT3992
pin FuncTions SHDN1/2:
The shutdown pin is used to control each
TJ:
The TJ pin outputs a voltage proportional to junction channel’s operation. In addition to controlling channel 1, temperature. The pin is 250mV for 25°C and has a slope the SHDN1 pin also activates control circuitry for both of 10mV/°C. See the Applications Information section for channels and must be present for channel 2 to operate. more information. When SHDN1 is below its threshold, quiescent current is
V
reduced to a typical value of 6µA. Independent channel
C1/2:
The VC pin is the output of the error amplifier and the input to the peak switch current comparator. It is normally UVLO can be programmed by connecting the SHDN pin to used for frequency compensation, but can also be used an input voltage divider. See the Applications Information as a current clamp or control loop override. If the error section for more information. If the shutdown features are amplifier drives V not used, the SHDN pin should be tied to V C above the maximum switch current IN. level, a voltage clamp activates. This indicates that the
SS1/2:
Current flowing out the SS pin into an external output is overloaded and current is pulled from the SS capacitor defines the rise time of the output voltage. When pin reducing the regulation point. the SS pin is lower than the 0.806V reference, the feedback
V
is regulated to the SS voltage. When the SS pin exceeds
IN1:
The VIN1 pin powers the internal control circuitry for both channels and is monitored by an undervoltage the reference voltage, the output will regulate the FB pin lockout comparator. The V voltage to 0.806V and the SS pin will continue to rise until IN1 pin is also connected to the collector of channel 1’s on-chip power NPN switch. The its clamp voltage. During an output overload, the VC pin is V driven above the maximum switch current level activating IN1 pin has high dI/dt edges and must be decoupled to ground close to the pin of the device. its voltage clamp. When the VC clamp is activated, the SS pin is discharged until the output reaches a regulation point
VIN2:
The VIN2 pin powers the output stage for channel 2 that the maximum output current can maintain. When the and is monitored by an undervoltage lockout comparator. overload condition is removed, the output soft starts from VIN1 voltage must be greater than typically 2.9V for VIN2 that voltage. In the case of a SHDN or thermal shutdown operation. The VIN2 pin is also the collector of channel event, a power on reset latch ensures the capacitors on 2’s on-chip power NPN switch. The VIN2 pin has high dI/ both channels are fully discharged before either is released. dt edges and must be decoupled to ground close to the Connecting both SS pins together ensures the outputs pin of the device. track together.
VOUT1/2:
The VOUT pin is the output to the internal sense
CLKOUT:
The CLKOUT pin generates a square wave of 0V resistor that measures current flowing in the inductor. to 2.5V which is synchronized to the internal oscillator. If When the current in the resistor exceeds the current dic- the switching frequency is set by an external resistor the tated by the VC pin, the SW latch is held in reset disabling resultant clock duty cycle will be 50%. If the RT/SYNC pin the output switch. Bias current flows out of the VOUT pin. is driven by an external clock source, the resultant CLKOUT duty cycle will mirror the external source.
SW1/2:
The SW pin is the emitter of the internal power NPN. At switch off, the inductor will drive this pin below ground with a high dV/dt. An external Schottky catch diode to ground, close to the SW pin and respective VIN decoupling capacitor’s ground, must be used to prevent this pin from excessive negative voltages. 3992fa For more information www.linear.com/LT3992 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
pin FuncTions SHDN1/2:
The shutdown pin is used to control each
TJ:
The TJ pin outputs a voltage proportional to junction channel’s operation. In addition to controlling channel 1, temperature. The pin is 250mV for 25°C and has a slope the SHDN1 pin also activates control circuitry for both of 10mV/°C. See the Applications Information section for channels and must be present for channel 2 to operate. more information. When SHDN1 is below its threshold, quiescent current is
V
reduced to a typical value of 6µA. Independent channel
C1/2:
The VC pin is the output of the error amplifier and the input to the peak switch current comparator. It is normally UVLO can be programmed by connecting the SHDN pin to used for frequency compensation, but can also be used an input voltage divider. See the Applications Information as a current clamp or control loop override. If the error section for more information. If the shutdown features are amplifier drives V not used, the SHDN pin should be tied to V C above the maximum switch current IN. level, a voltage clamp activates. This indicates that the
SS1/2:
Current flowing out the SS pin into an external output is overloaded and current is pulled from the SS capacitor defines the rise time of the output voltage. When pin reducing the regulation point. the SS pin is lower than the 0.806V reference, the feedback
V
is regulated to the SS voltage. When the SS pin exceeds
IN1:
The VIN1 pin powers the internal control circuitry for both channels and is monitored by an undervoltage the reference voltage, the output will regulate the FB pin lockout comparator. The V voltage to 0.806V and the SS pin will continue to rise until IN1 pin is also connected to the collector of channel 1’s on-chip power NPN switch. The its clamp voltage. During an output overload, the VC pin is V driven above the maximum switch current level activating IN1 pin has high dI/dt edges and must be decoupled to ground close to the pin of the device. its voltage clamp. When the VC clamp is activated, the SS pin is discharged until the output reaches a regulation point
VIN2:
The VIN2 pin powers the output stage for channel 2 that the maximum output current can maintain. When the and is monitored by an undervoltage lockout comparator. overload condition is removed, the output soft starts from VIN1 voltage must be greater than typically 2.9V for VIN2 that voltage. In the case of a SHDN or thermal shutdown operation. The VIN2 pin is also the collector of channel event, a power on reset latch ensures the capacitors on 2’s on-chip power NPN switch. The VIN2 pin has high dI/ both channels are fully discharged before either is released. dt edges and must be decoupled to ground close to the Connecting both SS pins together ensures the outputs pin of the device. track together.
VOUT1/2:
The VOUT pin is the output to the internal sense
CLKOUT:
The CLKOUT pin generates a square wave of 0V resistor that measures current flowing in the inductor. to 2.5V which is synchronized to the internal oscillator. If When the current in the resistor exceeds the current dic- the switching frequency is set by an external resistor the tated by the VC pin, the SW latch is held in reset disabling resultant clock duty cycle will be 50%. If the RT/SYNC pin the output switch. Bias current flows out of the VOUT pin. is driven by an external clock source, the resultant CLKOUT duty cycle will mirror the external source.
SW1/2:
The SW pin is the emitter of the internal power NPN. At switch off, the inductor will drive this pin below ground with a high dV/dt. An external Schottky catch diode to ground, close to the SW pin and respective VIN decoupling capacitor’s ground, must be used to prevent this pin from excessive negative voltages. 3992fa For more information www.linear.com/LT3992 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts