Datasheet LT1122 (Analog Devices) - 8

LT1122
APPLICATIONS INFORMATION Settling Time Measurements
The power supply connections to the LT1122 must maintain Settling time test circuits shown on some competitive a low impedance to ground over a bandwidth of 20MHz. devices’ data sheets require: This is especially important when driving a significant resistive or capacitive load, since all current delivered to 1. A “flat top” pulse generator. Unfortunately, flat top pulse the load comes from the power supplies. Multiple high generators are not commercially available. quality bypass capacitors are recommended for each power 2. A variable feedback capacitor around the device under supply line in any critical application. A 0.1µF ceramic and test. This capacitor varies over a four-to-one range. a 1µF electrolytic capacitor, as shown, placed as close as Presumably, as each op amp is measured for settling possible to the amplifier (with short lead lengths to power time, the capacitor is fine tuned to optimize settling supply common) will assure adequate high frequency time for that particular device. bypassing, in most applications. 3. A small inductor load to optimize settling. V+ + The LT1122’s settling time is 100% tested in the test circuit 1µF 0.1µF 7 shown. No “flat top” pulse generator is required. The test 2 – circuit can be readily constructed, using commercially 6 LT1122 available ICs. Of course, standard high frequency board 3 + construction techniques should be followed. All LT1122s 4 are measured with a constant feedback capacitor. No fine 1µF tuning is required. + 0.1µF V– 1122 TA03
Speed Boost/Overcompensation Terminal
When the feedback around the op amp is resistive (RF), Pin 8 of the LT1122 can be used to change the input stage a pole will be created with RF, the source resistance and operating current of the device. Shorting Pin 8 to the posi- capacitance (RS, CS), and the amplifier input capacitance tive supply (Pin 7) increases slew rate and bandwidth by (CIN ≈ 4pF). In low closed-loop gain configurations and about 25%, but at the expense of a reduction in phase with RS and RF in the kilohm range, this pole can create margin by approximately 18 degrees. Unity-gain capacitive excess phase shift and even oscillation. A small capaci- load handling decreases from typically 500pF to 100pF. tor (CF) in parallel with RF eliminates this problem. With R Conversely, connecting a 15k resistor from Pin 8 to ground S (CS + CIN) = RFCF, the effect of the feedback pole is completely removed. pulls 1mA out of Pin 8 (with V+ = 15V). This reduces slew rate and bandwidth by 25%. Phase margin and capacitive CF load handling improve; the latter typically increasing to 800pF. RF
High Speed Operation
– As with most high speed amplifiers, care should be CIN OUTPUT R taken with supply decoupling, lead dress and component S CS + placement. 1122 TA04 1122fb 8 For more information www.linear.com/LT1122