Datasheet LTC2051, LTC2052 (Analog Devices) - 8

LTC2051/LTC2052
U U W U APPLICATIO S I FOR ATIO Shutdown
To reduce this form of clock feedthrough, use smaller valued gain setting resistors and minimize the source The LTC2051 includes a shutdown pin in the 10-lead resistance at the input. If the resistance seen at the inputs MSOP. When this active low pin is high or allowed to float, is less than 10k, this form of clock feedthrough is less the device operates normally. When the shutdown pin is than 1 pulled low, the device enters shutdown mode; supply μVRMS input referred at 7.5kHz, or less than the amount of residue clock feedthrough from the first form current drops to 3μA, all clocking stops and the output previously described. assumes a high impedance state. Placing a capacitor across the feedback resistor reduces
Clock Feedthrough, Input Bias Current
either form of clock feedthrough by limiting the bandwidth The LTC2051/LTC2052 use autozeroing circuitry to achieve of the closed-loop gain. an almost zero DC offset over temperature, common Input bias current is defined as the DC current into the mode voltage and power supply voltage. The frequency of input pins of the op amp. The same current spikes that the clock used for autozeroing is typically 7.5kHz. The cause the second form of clock feedthrough previously term clock feedthrough is broadly used to indicate visibil- described, when averaged, dominate the DC input bias ity of this clock frequency in the op amp output spectrum. current of the op amp below 70°C. There are typically two types of clock feedthrough in At temperatures above 70 autozeroed op amps like the LTC2051/LTC2052. °C, the leakage of the ESD protection diodes on the inputs increase the input bias The first form of clock feedthough is caused by the settling currents of both inputs in the positive direction, while the of the internal sampling capacitor and is input referred; current caused by the charge injection stays relatively that is, it is multiplied by the closed-loop gain of the op constant. At elevated temperatures (above 85°C) the amp. This form of clock feedthrough is independent of the leakage current begins to dominate and both the negative magnitude of the input source resistance or the magnitude and positive pin’s input bias currents are in the positive of the gain setting resistors. The LTC2051/LTC2052 have direction (into the pins). a residue clock feedthrough of less than 1μVRMS input referred at 7.5kHz.
Input Pins, ESD Sensitivity
The second form of clock feedthrough is caused by the ESD voltages above 700V on the input pins of the op amp small amount of charge injection occurring during the will cause the input bias currents to increase (more DC sampling and holding of the op amps input offset voltage. current into the pins). At these voltages, it is possible to The current spikes are multiplied by the impedance seen damage the device to a point where the input bias current at the input terminals of the op amp, appearing at the exceeds the maximums specified in this data sheet. output multiplied by the closed-loop gain of the op amp.
U TYPICAL APPLICATIO
The dual chopper op amp buffers the inputs of A1 and needed and the input source resistance is low. (For in- corrects its offset voltage and offset voltage drift. With the stance a 350Ω strain gauge bridge.) The LT1012 or RC values shown, the power-up warm-up time is typically equivalent should be used when low bias current (100pA) 20 seconds. The step response of the composite amplifier is also required in conjunction with DC to 10Hz low noise, does not present settling tails. The LT®1677 should be low VOS and VOS drift. The measured typical input offset used when extremely low noise, VOS and VOS drift are voltages are less than 1μV. 20512fd 8