Datasheet ADE7758 (Analog Devices) - 6

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ADE7758 Data Sheet Parameter1,
2
Specification Unit Test Conditions/Comments
LOGIC OUTPUTS DVDD = 5 V ± 5% IRQ, DOUT, and CLKOUT IRQ is open-drain, 10 kΩ pull-up resistor Output High Voltage, VOH 4 V min ISOURCE = 5 mA Output Low Voltage, VOL 0.4 V max ISINK = 1 mA APCF and VARCF Output High Voltage, VOH 4 V min ISOURCE = 8 mA Output Low Voltage, VOL 1 V max ISINK = 5 mA POWER SUPPLY For specified performance AVDD 4.75 V min 5 V − 5% 5.25 V max 5 V + 5% DVDD 4.75 V min 5 V − 5% 5.25 V max 5 V + 5% AIDD 8 mA max Typically 5 mA DIDD 13 mA max Typically 9 mA 1 See the Typical Performance Characteristics. 2 See the Terminology section for a definition of the parameters. 3 See the Analog Inputs section.
TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C.
Table 2. Parameter1, 2 Specification Unit Test Conditions/Comments
WRITE TIMING t1 50 ns (min) CS falling edge to first SCLK falling edge t2 50 ns (min) SCLK logic high pulse width t3 50 ns (min) SCLK logic low pulse width t4 10 ns (min) Valid data setup time before falling edge of SCLK t5 5 ns (min) Data hold time after SCLK falling edge t6 1200 ns (min) Minimum time between the end of data byte transfers t7 400 ns (min) Minimum time between byte transfers during a serial write t8 100 ns (min) CS hold time after SCLK falling edge READ TIMING t 3 9 4 μs (min) Minimum time between read command (that is, a write to communication register) and data read t10 50 ns (min) Minimum time between data byte transfers during a multibyte read t 4 11 30 ns (min) Data access time after SCLK rising edge following a write to the communications register t 5 12 100 ns (max) Bus relinquish time after falling edge of SCLK 10 ns (min) t 5 13 100 ns (max) Bus relinquish time after rising edge of CS 10 ns (min) 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2 See the timing diagrams in Figure 3 and Figure 4 and the Serial Interface section. 3 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min. 4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. 5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted here is the true bus relinquish time of the part and is independent of the bus loading. Rev. E | Page 6 of 72 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION ANTIALIASING FILTER ANALOG INPUTS CURRENT CHANNEL ADC Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR PEAK CURRENT DETECTION Peak Current Detection Using the PEAK Register OVERCURRENT DETECTION INTERRUPT VOLTAGE CHANNEL ADC Voltage Channel Sampling ZERO-CROSSING DETECTION Zero-Crossing Timeout PHASE COMPENSATION PERIOD MEASUREMENT LINE VOLTAGE SAG DETECTION SAG LEVEL SET PEAK VOLTAGE DETECTION Peak Voltage Detection Using the VPEAK Register Overvoltage Detection Interrupt PHASE SEQUENCE DETECTION POWER-SUPPLY MONITOR REFERENCE CIRCUIT TEMPERATURE MEASUREMENT ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Voltage RMS Gain Adjust ACTIVE POWER CALCULATION Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation No-Load Threshold Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Active Power Frequency Output Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Reactive Power Frequency Output Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Apparent Power Frequency Output Line Cycle Apparent Energy Accumulation Mode ENERGY REGISTERS SCALING WAVEFORM SAMPLING MODE CALIBRATION Calibration Using Pulse Output Gain Calibration Using Pulse Output Example: Watt Gain Calibration of Phase A Using Pulse Output Phase Calibration Using Pulse Output Example: Phase Calibration of Phase A Using Pulse Output Power Offset Calibration Using Pulse Output Example: Offset Calibration of Phase A Using Pulse Output Calibration Using Line Accumulation Gain Calibration Using Line Accumulation Example: Watt Gain Calibration Using Line Accumulation Phase Calibration Using Line Accumulation Example: Phase Calibration Using Line Accumulation Power Offset Calibration Using Line Accumulation Example: Power Offset Calibration Using Line Accumulation Calibration of IRMS and VRMS Offset Example: Calibration of RMS Offsets CHECKSUM REGISTER INTERRUPTS USING THE INTERRUPTS WITH AN MCU INTERRUPT TIMING SERIAL INTERFACE SERIAL WRITE OPERATION SERIAL READ OPERATION ACCESSING THE ON-CHIP REGISTERS REGISTERS COMMUNICATIONS REGISTER OPERATIONAL MODE REGISTER (0x13) MEASUREMENT MODE REGISTER (0x14) WAVEFORM MODE REGISTER (0x15) COMPUTATIONAL MODE REGISTER (0x16) LINE CYCLE ACCUMULATION MODE REGISTER (0x17) INTERRUPT MASK REGISTER (0x18) INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A) OUTLINE DIMENSIONS ORDERING GUIDE