Datasheet ADE7758 (Analog Devices) - 5

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Data Sheet ADE7758 SPECIFICATIONS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C.
Table 1. Parameter1,
2
Specification Unit Test Conditions/Comments
ACCURACY Active Energy Measurement Error 0.1 % typ Over a dynamic range of 1000 to 1 (per Phase) Phase Error Between Channels Line frequency = 45 Hz to 65 Hz, HPF on PF = 0.8 Capacitive ±0.05 °max Phase lead 37° PF = 0.5 Inductive ±0.05 °max Phase lag 60° AC Power Supply Rejection AVDD = DVDD = 5 V + 175 mV rms/120 Hz Output Frequency Variation 0.01 % typ V1P = V2P = V3P = 100 mV rms DC Power Supply Rejection AVDD = DVDD = 5 V ± 250 mV dc Output Frequency Variation 0.01 % typ V1P = V2P = V3P = 100 mV rms Active Energy Measurement Bandwidth 14 kHz IRMS Measurement Error 0.5 % typ Over a dynamic range of 500:1 IRMS Measurement Bandwidth 14 kHz VRMS Measurement Error 0.5 % typ Over a dynamic range of 20:1 VRMS Measurement Bandwidth 260 Hz ANALOG INPUTS See the Analog Inputs section Maximum Signal Levels ±500 mV max Differential input Input Impedance (DC) 380 kΩ min ADC Offset Error3 ±30 mV max Uncalibrated error, see the Terminology section Gain Error3 ±6 % typ External 2.5 V reference WAVEFORM SAMPLING Sampling CLKIN/128, 10 MHz/128 = 78.1 kSPS Current Channels See the Current Channel ADC section Signal-to-Noise Plus Distortion 62 dB typ Bandwidth (−3 dB) 14 kHz Voltage Channels See the Voltage Channel ADC section Signal-to-Noise Plus Distortion 62 dB typ Bandwidth (−3 dB) 260 Hz REFERENCE INPUT REFIN/OUT Input Voltage Range 2.6 V max 2.4 V + 8% 2.2 V min 2.4 V − 8% Input Capacitance 10 pF max ON-CHIP REFERENCE Nominal 2.4 V at REFIN/OUT pin Reference Error ±200 mV max Current Source 6 μA max Output Impedance 4 kΩ min Temperature Coefficient 30 ppm/°C typ CLKIN All specifications CLKIN of 10 MHz Input Clock Frequency 15 MHz max 5 MHz min LOGIC INPUTS DIN, SCLK, CLKIN, and CS Input High Voltage, VINH 2.4 V min DVDD = 5 V ± 5% Input Low Voltage, VINL 0.8 V max DVDD = 5 V ± 5% Input Current, IIN ±3 μA max Typical 10 nA, VIN = 0 V to DVDD Input Capacitance, CIN 10 pF max Rev. E | Page 5 of 72 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION ANTIALIASING FILTER ANALOG INPUTS CURRENT CHANNEL ADC Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR PEAK CURRENT DETECTION Peak Current Detection Using the PEAK Register OVERCURRENT DETECTION INTERRUPT VOLTAGE CHANNEL ADC Voltage Channel Sampling ZERO-CROSSING DETECTION Zero-Crossing Timeout PHASE COMPENSATION PERIOD MEASUREMENT LINE VOLTAGE SAG DETECTION SAG LEVEL SET PEAK VOLTAGE DETECTION Peak Voltage Detection Using the VPEAK Register Overvoltage Detection Interrupt PHASE SEQUENCE DETECTION POWER-SUPPLY MONITOR REFERENCE CIRCUIT TEMPERATURE MEASUREMENT ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Voltage RMS Gain Adjust ACTIVE POWER CALCULATION Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation No-Load Threshold Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Active Power Frequency Output Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Reactive Power Frequency Output Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Apparent Power Frequency Output Line Cycle Apparent Energy Accumulation Mode ENERGY REGISTERS SCALING WAVEFORM SAMPLING MODE CALIBRATION Calibration Using Pulse Output Gain Calibration Using Pulse Output Example: Watt Gain Calibration of Phase A Using Pulse Output Phase Calibration Using Pulse Output Example: Phase Calibration of Phase A Using Pulse Output Power Offset Calibration Using Pulse Output Example: Offset Calibration of Phase A Using Pulse Output Calibration Using Line Accumulation Gain Calibration Using Line Accumulation Example: Watt Gain Calibration Using Line Accumulation Phase Calibration Using Line Accumulation Example: Phase Calibration Using Line Accumulation Power Offset Calibration Using Line Accumulation Example: Power Offset Calibration Using Line Accumulation Calibration of IRMS and VRMS Offset Example: Calibration of RMS Offsets CHECKSUM REGISTER INTERRUPTS USING THE INTERRUPTS WITH AN MCU INTERRUPT TIMING SERIAL INTERFACE SERIAL WRITE OPERATION SERIAL READ OPERATION ACCESSING THE ON-CHIP REGISTERS REGISTERS COMMUNICATIONS REGISTER OPERATIONAL MODE REGISTER (0x13) MEASUREMENT MODE REGISTER (0x14) WAVEFORM MODE REGISTER (0x15) COMPUTATIONAL MODE REGISTER (0x16) LINE CYCLE ACCUMULATION MODE REGISTER (0x17) INTERRUPT MASK REGISTER (0x18) INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A) OUTLINE DIMENSIONS ORDERING GUIDE