Datasheet ADE7880 (Analog Devices) - 3

Data Sheet ADE7880 REVISION HISTORY 12/14—Rev. B to Rev. C
Changes to Power Factor Calculation Section and Harmonics Changes to Pin EP, Table 7 ... 13 Calculations Section ... 58 Changes to Configuring Harmonic Calculations Update Changes to Figure 85 .. 60 Rate Section .. 66 Changes to Energy-to-Frequency Conversion Section .. 66 Change to Address 0x43C7, Table 30 ... 88 Changes to Checksum Register Section, Equation 54, and Changes to Bit 19, Table 36 .. 94 Figure 100 ... 73 Changes to Bit 19, Table 38 .. 97 Changes to Table 24 .. 75 Changes to I2C-Compatible Interface Section .. 76
8/14—Rev. A to Rev. B
Changes to Figure 109 .. 80 Change to Features Section .. 1 Changes to ADE7880 Quick Setup as Energy Meter Section ... 82 Changes to Patent Footnote ... 1 Added Layout Guidelines Section... 83 Changes to Functional Block Diagram .. 4 Added Crystal Circuit Section .. 84 Changes to Table 1 .. 5 Changes to Silicon Anomaly Section, Table 26, and Table 27 ... 85 Changes to Data Hold Time Parameter, Table 2, and Figure 2 ... 8 Changes to Table 30 .. 87 Changes to Pin 5 and Pin 24, Table 7, and Figure 6 ... 12 Changes to Table 33 .. 90 Changes to Figure 16 and Figure 18 ... 15 Changes to Bit 19, Table 36 .. 94 Changes to Figure 20 and Figure 24 Caption .. 16 Changes to Bit 19, Table 38 .. 97 Moved Figure 29 and Figure 30 ... 18 Changes to Table 42 .. 99 Changes to Test Circuit Section and Figure 32 ... 19 Changes to Table 45 .. 101 Changes to Terminology Section .. 20 Changes to Table 50 .. 104 Changes to PSM2—Low Power Mode Section ... 21 Changes to Bits[4:3], Table 54 ... 106 Added Figure 34; Renumbered Sequentially ... 22 Change to Power-Up Procedure Section and Figure 35 .. 24
3/12—Rev. 0 to Rev. A
Changes to Figure 42 and Figure 43 ... 28 Removed References to + N (Plus Noise) and changed VTHDN Changes to Figure 48 and Figure 50; Added Figure 49 .. 30 to VTHD and ITHDN to ITHD .. Throughout Changes to Changing Phase Voltage Data Path Section and Changes to Reactive Energy Management Parameter in Table 1 4 Figure 51 ... 31 Changes to Figure 6 .. 11 Changes to Power Quality Measurements Section and Changes to Table 7 .. 12 Figure 52 ... 32 Changes to Phase Compensation Section .. 36 Changed ADCMAX = 5,928,256, to ADCMAX = 5,326,737, Changes to Equation 13 ... 39 Neutral Current Mismatch Section... 37 Changes to Equation 33 ... 49 Added Figure 64 .. 38 Changes to Fundamental Reactive Energy Calculation Changes to Reference Circuit Section and Digital Signal Section .. 51 Processor Section .. 39 Changes to Figure 80 .. 55 Changes to Current RMS Calculation Section .. 41 Changes to Figure 85 .. 62 Changes to Voltage RMS Offset Compensation Section, Changes to Energy Registers and CF Outputs for Various Voltage RMS in 3-Phase, 3-Wire Delta Configurations Section, Accumulation Modes Section ... 67 and Active Power Calculation Section ... 45 Changes to Figure 95 .. 69 Changes to Figure 76 .. 46 Changes to No Load Condition Section .. 69 Changes to Fundamental Active Power Calculation Section ... 47 Changes to Equation 53 ... 71 Added Managing Change in Fundamental Line Frequency Changes to Figure 100 .. 74 Section .. 47 Changes to Figure 101 and to Figure 102 .. 75 Changes to Figure 78 .. 49 Changes to SPI-Compatible Interface Section .. 76 Changes to Active Energy Accumulation Modes Section ... 50 Changes to HSDC Interface Section... 78 Changes to Fundamental Reactive Power Calculation Section Changes to Figure 109 and to Figure 110 .. 80 and Equation 35 ... 51 Changes to Silicon Anomaly Section ... 81 Changes to Fundamental Reactive Energy Accumulation Changes to Table 48 .. 99 Modes Section .. 54 Changes to Table 52 .. 101 Changes to Apparent Power Calculation Section ... 55 Changes to Apparent Energy Accumulation Modes Section
10/11—Revision 0: Initial Version
and Figure 83 ... 57 Rev. C | Page 3 of 107 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY POWER MANAGEMENT PSM0—NORMAL POWER MODE (ALL PARTS) PSM1—REDUCED POWER MODE PSM2—LOW POWER MODE PSM3—SLEEP MODE (ALL PARTS) POWER-UP PROCEDURE HARDWARE RESET SOFTWARE RESET FUNCTIONALITY THEORY OF OPERATION ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function CURRENT CHANNEL ADC Current Waveform Gain Registers Current Channel HPF Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR VOLTAGE CHANNEL ADC Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling CHANGING PHASE VOLTAGE DATA PATH POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Period Measurement Phase Voltage Sag Detection Sag Level Set Peak Detection Overvoltage and Overcurrent Detection Overvoltage and Overcurrent Level Set Neutral Current Mismatch PHASE COMPENSATION REFERENCE CIRCUIT DIGITAL SIGNAL PROCESSOR ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Offset Compensation Current Mean Absolute Value Calculation Current MAV Gain and Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Voltage RMS in 3-Phase, 3-Wire Delta Configurations ACTIVE POWER CALCULATION Total Active Power Calculation Fundamental Active Power Calculation Managing Change in Fundamental Line Frequency Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Active Energy Accumulation Modes Line Cycle Active Energy Accumulation Mode FUNDAMENTAL REACTIVE POWER CALCULATION Fundamental Reactive Power Gain Calibration Fundamental Reactive Power Offset Calibration Sign of Fundamental Reactive Power Calculation Fundamental Reactive Energy Calculation Integration Time Under Steady Load Fundamental Reactive Energy Accumulation Modes Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Apparent Energy Accumulation Modes Line Cycle Apparent Energy Accumulation Mode POWER FACTOR CALCULATION HARMONICS CALCULATIONS Harmonics Calcuations Theory Configuring the Harmonic Calculations Harmonic Calculations When a Phase is Monitored Harmonic Calculations When the Neutral is Monitored Configuring Harmonic Calculations Update Rate Recommended Approach to Managing Harmonic Calculations WAVEFORM SAMPLING MODE ENERGY-TO-FREQUENCY CONVERSION Synchronizing Energy Registers with CFx Outputs Energy Registers and CF Outputs for Various Accumulation Modes Sign of Sum of Phase Powers in the CFx Data Path NO LOAD CONDITION No Load Detection Based On Total Active Power and Apparent Power No Load Detection Based on Fundamental Active and Reactive Powers No Load Detection Based on Apparent Power CHECKSUM REGISTER INTERRUPTS Using the Interrupts with an MCU SERIAL INTERFACES Serial Interface Choice Communication Verification I2C-Compatible Interface I2C Write Operation I2C Read Operation I2C Read Operation of Harmonic Calculations Registers SPI-Compatible Interface SPI Read Operation SPI Read Operation of Harmonic Calculations Registers SPI Write Operation HSDC Interface ADE7880 QUICK SETUP AS ENERGY METER LAYOUT GUIDELINES CRYSTAL CIRCUIT ADE7880 EVALUATION BOARD DIE VERSION SILICON ANOMALY ADE7880 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADE7880 FUNCTIONALITY ISSUES REGISTERS LIST OUTLINE DIMENSIONS ORDERING GUIDE