Datasheet ADE9000 (Analog Devices) - 9

Data Sheet ADE9000 ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE Table 3.
Thermal performance is directly linked to printed circuit board
Parameter Rating
(PCB) design and operating environment. Careful attention to VDD to GND −0.3 V to +3.96 V PCB thermal design is required. Analog Input Voltage to GND, IAP, IAN, IBP, −2 V to +2 V θJA and θJC are specified for the worst case conditions, that is, a IBN, ICP, ICN, VAP, VAN, VBP, VBN, VCP, VCN device soldered in a circuit board for surface-mount packages. Reference Input Voltage to REFGND −0.3 V to +2 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Table 4. Thermal Resistance
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Package Type θJA θJC Unit
Operating Temperature CP-40-71 27.14 3.13 °C/W Industrial Range −40°C to +85°C 1 The junction to air measurement uses a 2S2P JEDEC test board with 4 × 4 Storage Temperature Range −65°C to +150°C standard JEDEC vias. The junction to case measurement uses a 1S0P JEDEC test Junction Temperature 125°C board with 4 × 4 standard JEDEC vias. See JEDEC standard JESD51-2. Lead Temperature (Soldering, 10 sec)1 260°C ESD
ESD CAUTION
Human Body Model2 4 kV Machine Model3 300 V Field Induced Charged Device Model 1.25 kV (FICDM) 4 1 Analog Devices recommends that reflow profiles used in soldering RoHS compliant devices conform to J-STD-020D.1 from JEDEC. Refer to JEDEC for the latest revision of this standard. 2 Applicable standard: ANSI/ESDA/JEDEC JS-001-2014. 3 Applicable standard: JESD22-A115-A (ESD machine model standard of JEDEC). 4 Applicable standard: JESD22-C101F (ESD FICDM standard of JEDEC). Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 9 of 72 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY TYPICAL APPLICATIONS CIRCUIT SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE ENERGY ERROR OVER FREQUENCY AND POWER FACTOR ENERGY LINEARITY REPEATABILITY RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY ENERGY AND RMS LINEARITY WITH INTEGRATOR ON ENERGY AND RMS ERROR OVER FREQUENCY WITH INTEGRATOR ON SIGNAL-TO-NOISE RATIO PERFORMANCE TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION MEASUREMENTS Current Channel ADC_REDIRECT Multiplexer Current Channel Gain, xIGAIN IB Calculation Using ICONSEL High-Pass Filter Digital Integrator Phase Compensation Multipoint Phase and Gain Calibration Voltage Channel RMS and Power Measurements Total and Fundamental RMS Total and Fundamental Active Power Total and Fundamental Reactive Power Total and Fundamental Apparent Power No Load Detection, Energy Accumulation, and Power Accumulation Features No Load Detection Feature Energy Accumulation Power Accumulation Digital to Frequency Conversion—CFx Output Energy and Phase Selection Configuring the CFx Pulse Width CFx Pulse Sign Clearing the CFx Accumulator POWER QUALITY MEASUREMENTS Zero-Crossing Detection CF3/ZX Zero-Crossing Timeout Line Period Calculation Angle Measurement Phase Sequence Error Detection Fast RMS½ Measurement 10 Cycle RMS/12 Cycle RMS Dip and Swell Indication Overcurrent Indication Peak Detection Power Factor Total Harmonic Distortion (THD) Resampling 128 Points per Cycle Temperature WAVEFORM BUFFER INTERRUPTS/EVENTS ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW ADDITIONAL COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK REGISTER MAP REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE