Datasheet ADR03-EP (Analog Devices) - 6

ADR03-EP Enhanced Product OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 5 4 2.40 1.25 2.10 1.15 1 2 3 1.80 0.65 BSC 1.00 1.10 0.40 0.90 0.80 0.10 0.70 0.46 0.22 0.10 MAX SEATING 0.30 0.36 PLANE 0.08 COPLANARITY 0.15 0.26 0.10 -A 9 0 8 2 COMPLIANT TO JEDEC STANDARDS MO-203-AA 7 0
Figure 7. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters
ORDERING GUIDE Output Initial Temperature Voltage Accuracy Coefficient Temperature Package Package Ordering Marking Model1 VO (V) (mV) (%) (ppm/°C) Range Description Option Quantity Code
ADR03TKSZ-EP-R7 2.5 5 0.2 30 −55°C to +125°C 5-Lead SC70 KS-5 3,000 R3N 1 Z = RoHS Compliant Part.
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Rev. 0 | Page 6 of 6 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE