Preliminary Datasheet ADAR1000 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 4 Channel X/Ku Band Beamformer |
| Seiten / Seite | 51 / 9 — Preliminary Technical Data. ADAR1000. PIN CONFIGURATION AND FUNCTION … |
| Revision | PrF |
| Dateiformat / Größe | PDF / 1.2 Mb |
| Dokumentensprache | Englisch |
Preliminary Technical Data. ADAR1000. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. Table 4. Pin Function Descriptions. Pin No
Textversion des Dokuments
Preliminary Technical Data ADAR1000 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. Pinout
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
A2, A6, A8, A12, A13, B1, GND RF Ground. All ground pins should be tied together. B2, B6-B10, B12, B13, C2, C12, D1, D2, D12, D13, E2, E12, F1, F2, F12, F13, G2, G12, H1, H2, H12, H13, J2, J12, K1, K2, K12, K13, L2, L12, M1, M2, M7, M12, M13, N1, N7, N8, N12 A1 DET3 Channel 3 power detector input A3 TR_SW_NEG Gate control output for external T/R switch (0 or -5V) A4 PA_BIAS4 Gate Bias for external PA A5 PA_BIAS3 Gate Bias for external PA A7 RF_IO Common RF pin for TX Input and RX Output A9 PA_BIAS2 Gate Bias for external PA A10 PA_BIAS1 Gate Bias for external PA A11 LNA_BIAS Gate Bias for external LNA B3 PA_ON PA enable output; must be at logic high for PA Bias voltages to assume values set by EXT_PAx_BIAS_ON registers (x=1 to 4) B4 TR_POL Output to control external polarization switch (0 or -5V) B5 TR_SW_POS Output to control external T/R switch (0 or +3.3V) B11 AVDD1 -5V Power Supply C1 TX3 Channel 3 TX output C13 RX2 Channel 2 RX input E1 RX3 Channel 3 RX input E13 TX2 Channel 2 TX output G1 DET4 Channel 4 power detector input G13 DET2 Channel 2 power detector input J1 TX4 Channel 4 TX output Rev. PrF| Page 9 of 51 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Specifications Timing Diagram SPI Block Write Mode Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Changes from Previous Silicon Revision T/R switch driver output External PA and LNA bias DACs Eliminated the -3.3V supply input to the chip New PA_ON input pin Applications Gain Control Registers Switched Attenuator Control TR_SW_POS and TR_SW_NEG (T/R Switch Control) TX/RX Subcircuit Control TR_SOURCE = 0 SPI Programming Example Register Maps Address: 0x000, Reset: 0x00, Name: INTERFACE_CONFIG_A Outline Dimensions
Figure 6. Pinout
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
A2, A6, A8, A12, A13, B1, GND RF Ground. All ground pins should be tied together. B2, B6-B10, B12, B13, C2, C12, D1, D2, D12, D13, E2, E12, F1, F2, F12, F13, G2, G12, H1, H2, H12, H13, J2, J12, K1, K2, K12, K13, L2, L12, M1, M2, M7, M12, M13, N1, N7, N8, N12 A1 DET3 Channel 3 power detector input A3 TR_SW_NEG Gate control output for external T/R switch (0 or -5V) A4 PA_BIAS4 Gate Bias for external PA A5 PA_BIAS3 Gate Bias for external PA A7 RF_IO Common RF pin for TX Input and RX Output A9 PA_BIAS2 Gate Bias for external PA A10 PA_BIAS1 Gate Bias for external PA A11 LNA_BIAS Gate Bias for external LNA B3 PA_ON PA enable output; must be at logic high for PA Bias voltages to assume values set by EXT_PAx_BIAS_ON registers (x=1 to 4) B4 TR_POL Output to control external polarization switch (0 or -5V) B5 TR_SW_POS Output to control external T/R switch (0 or +3.3V) B11 AVDD1 -5V Power Supply C1 TX3 Channel 3 TX output C13 RX2 Channel 2 RX input E1 RX3 Channel 3 RX input E13 TX2 Channel 2 TX output G1 DET4 Channel 4 power detector input G13 DET2 Channel 2 power detector input J1 TX4 Channel 4 TX output Rev. PrF| Page 9 of 51 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Specifications Timing Diagram SPI Block Write Mode Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Changes from Previous Silicon Revision T/R switch driver output External PA and LNA bias DACs Eliminated the -3.3V supply input to the chip New PA_ON input pin Applications Gain Control Registers Switched Attenuator Control TR_SW_POS and TR_SW_NEG (T/R Switch Control) TX/RX Subcircuit Control TR_SOURCE = 0 SPI Programming Example Register Maps Address: 0x000, Reset: 0x00, Name: INTERFACE_CONFIG_A Outline Dimensions