Datasheet TPS2410, TPS2411 (Texas Instruments) - 9
Hersteller | Texas Instruments |
Beschreibung | Full Feaured N+1 and ORing Power Rail Controller |
Seiten / Seite | 32 / 9 — TPS2410. TPS2411. www.ti.com. TYPICAL CHARACTERISTICS. TPS2410 V(AC) … |
Revision | C |
Dateiformat / Größe | PDF / 1.4 Mb |
Dokumentensprache | Englisch |
TPS2410. TPS2411. www.ti.com. TYPICAL CHARACTERISTICS. TPS2410 V(AC) REGULATION. VOLTAGE. FAST TURNOFF THRESHOLD
Modelllinie für dieses Datenblatt
Textversion des Dokuments
TPS2410 TPS2411 www.ti.com
.. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
TYPICAL CHARACTERISTICS TPS2410 V(AC) REGULATION VOLTAGE FAST TURNOFF THRESHOLD PULSED GATE SINKING CURRENT vs vs vs TEMPERATURE TEMPERATURE GATE VOLTAGE 12.0 5.0 3.0 R = Open (RSET) 11.5 4.5
T = -40oC J
2.5 11.0 4.0
T = 25oC J
2.0 10.5 3.5 A − mV
T = 85 C o
mV
J
− − TE) 10.0 ) 3.0 A 1.5 ) C C I (G (A (A V V 9.5 2.5
o
1.0
T = 125 C J
9.0 2.0 0.5 8.5 1.5 8.0 1.0 0.0 0 2 4 6 8 10 −40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 V − V (GATE - GND) T − Junction T J emperature − C o T − Junction T J emperature − C o Figure 2. Figure 3. Figure 4. TURNON DELAY vs VDD CURRENT VDD vs (POWER APPLIED UNTIL GATE IS VDD VOLTAGE ACTIVE) (GATE SATURATED HIGH) 60 3.0 50 2.5
T = -40 C o J
40 2.0
T = 25 C o J T = 125 C o
s
J m
mA
T = 25 C o
−
J
− 30 ) 1.5 D Delay I (VD 20 1.0
T = -40oC J T = 125 C o J
10 0.5 0 0.0 2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 16 18 V − V DD V − V DD Figure 5. Figure 6.
Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TPS2410 TPS2411 Document Outline FEATURES APPLICATIONS DESCRIPTION ABSOLUTE MAXIMUM RATINGS DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS: TPS2410/11 DETAILED DESCRIPTION TYPICAL CHARACTERISTICS APPLICATION INFORMATION OVERVIEW TPS2410 vs TPS2411 – MOSFET CONTROL METHODS N+1 POWER SUPPLY – TYPICAL CONNECTION INPUT ORing – TYPICAL CONNECTION SYSTEM DESIGN AND BEHAVIOR WITH TRANSIENTS RECOMMENDED OPERATING RANGE TPS2410 REGULATION-LOOP STABILITY MOSFET SELECTION AND R(RSET) GATE DRIVE, CHARGE PUMP AND C(BYP) FAST COMPARATOR INPUT FILTERING – C(FLTR) UV, OV, AND PG VDD, BYP, and POWERING OPTIONS INPUT ORing AND STAT BIDIRECTIONAL BLOCKING AND PROTECTION OF C ORing EXAMPLES SUMMARIZED DESIGN PROCEDURE Layout Considerations