Datasheet KSZ8873MLL, KSZ8873FLL, KSZ8873RLL (Microchip) - 9
| Hersteller | Microchip |
| Beschreibung | Integrated 3-Port 10/100 Managed Switch with PHYs |
| Seiten / Seite | 95 / 9 — KSZ8873MLL/FLL/RLL. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. … |
| Dateiformat / Größe | PDF / 1.4 Mb |
| Dokumentensprache | Englisch |
KSZ8873MLL/FLL/RLL. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. Description. Number. Name. 2-1. Port 1 LED Indicators:. Strap option:
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KSZ8873MLL/FLL/RLL TABLE 2-1: SIGNALS (CONTINUED) Type Pin Pin Note Description Number Name 2-1
PU = force port 3 to 10BT 51 P3SPD Ipd/O PD = force port 3 to 100BT (default) 52 NC NC Unused pin. No external connection. 53 NC NC Unused pin. No external connection. 3.3V, 2.5V or 1.8V digital V 54 VDDIO P DD input power supply for IO with well decoupling capacitors. 55 GND GND Digital ground 1.8V core power voltage output (internal 1.8V LDO regulator output), this 1.8V output pin provides power to both VDDA_1.8 and VDDC input pins. 56 VDDCO P Note: Internally 1.8V LDO regulator input comes from VDDIO. Do not connect an external power supply to VDDCO pin. The ferrite bead is requested between analog and digital 1.8V core power. 57 NC NC Unused pin. No external connection.
Port 1 LED Indicators:
Default: Speed (refer to register 195 bit[5:4]) 58 P1LED1 Ipu/O
Strap option:
Port 3 flow control selection (P3FFC) PU = always enable (force) port 3 flow control feature (default) PD = disable
Port 1 LED Indicators:
Default: Link/Act. (refer to Register 195 bit[5:4])
Strap option:
Port 3 duplex mode selection (P3DPX) 59 P1LED0 Ipd/O PU = port 3 to half-duplex mode PD = port 3 to full-duplex mode (default) Note: P1LED0 has weaker internal pull-down, recommend an external pull- down by a 0.5 kΩ resistor. 2017 Microchip Technology Inc. DS00002348A-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service
PU = force port 3 to 10BT 51 P3SPD Ipd/O PD = force port 3 to 100BT (default) 52 NC NC Unused pin. No external connection. 53 NC NC Unused pin. No external connection. 3.3V, 2.5V or 1.8V digital V 54 VDDIO P DD input power supply for IO with well decoupling capacitors. 55 GND GND Digital ground 1.8V core power voltage output (internal 1.8V LDO regulator output), this 1.8V output pin provides power to both VDDA_1.8 and VDDC input pins. 56 VDDCO P Note: Internally 1.8V LDO regulator input comes from VDDIO. Do not connect an external power supply to VDDCO pin. The ferrite bead is requested between analog and digital 1.8V core power. 57 NC NC Unused pin. No external connection.
Port 1 LED Indicators:
Default: Speed (refer to register 195 bit[5:4]) 58 P1LED1 Ipu/O
Strap option:
Port 3 flow control selection (P3FFC) PU = always enable (force) port 3 flow control feature (default) PD = disable
Port 1 LED Indicators:
Default: Link/Act. (refer to Register 195 bit[5:4])
Strap option:
Port 3 duplex mode selection (P3DPX) 59 P1LED0 Ipd/O PU = port 3 to half-duplex mode PD = port 3 to full-duplex mode (default) Note: P1LED0 has weaker internal pull-down, recommend an external pull- down by a 0.5 kΩ resistor. 2017 Microchip Technology Inc. DS00002348A-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service