Datasheet KSZ8873MLL, KSZ8873FLL, KSZ8873RLL (Microchip) - 4

KSZ8873MLL/FLL/RLL 1.0 INTRODUCTION 1.1 General Description
The KSZ8873MLL/FLL/RLL are highly integrated 3-port switch-on-a-chip ICs in the industry’s smallest footprint. They are designed to enable a new generation of low port count, cost-sensitive, and power efficient 10/100 Mbps switch sys- tems. Low power consumption, advanced power management, and sophisticated QoS features (e.g., IPv6 priority clas- sification support) make these devices ideal for IPTV, IP-STB, VoIP, automotive, and industrial applications. The KSZ8873 family is designed to support the GREEN requirement in today’s switch systems. Advanced power man- agement schemes include hardware power down, software power down, per port power down, and the energy detect mode that shuts downs the transceiver when a port is idle. KSZ8873MLL/FLL/RLL also offer a bypass mode. In this mode, the processor connected to the switch through the MII interface can be shut down without impacting the normal switch operation. The configurations provided by the KSZ8873 family enables the flexibility to meet requirements of different applications: • KSZ8873MLL: Two 10/100BASE-T/TX transceivers and one MII interface. • KSZ8873RLL: Two 10/100BASE-T/TX transceivers and one RMII interface. • KSZ8873FLL: Two 100BASE-FX transceivers and one MII interface. The devices are available in RoHS-compliant 64-pin LQFP packages. Industrial-grade and qualified AEC-Q100 Auto- motive-grade versions are also available.
FIGURE 1-1: SYSTEM BLOCK DIAGRAM
1K LOOK-UP F ENGINE 10/100 FI HP AUTO 10/100 O T/TX/FX MDIX MAC 1 F , PHY 1 L O QUEUE W MANAGEMENT 10/100 C HP AUTO 10/100 O T/TX/FX N MDIX MAC 2 T PHY 2 R BUFFER O L MANAGEMENT V , 10/100 L MII/SNI A MAC 3 N T FRAME A G BUFFERS G NI G P , MIB SPI SPI R COUNTERS OI R TI Y MIIM CONTROL EEPROM REGISTERS INTERFACE SMI I2C P1 LED[1:0] LED STRAP IN DRIVERS CONFIGURATION P2 LED[1:0] DS00002348A-page 4  2017 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service