Datasheet AD650 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Voltage-to-Frequency and Frequency-to-Voltage Converter |
| Seiten / Seite | 21 / 10 — Data Sheet. AD650. 1MHz. S 100kHz. L- L. INPUT. RESISTOR. Y C N. E U. … |
| Revision | E |
| Dateiformat / Größe | PDF / 454 Kb |
| Dokumentensprache | Englisch |
Data Sheet. AD650. 1MHz. S 100kHz. L- L. INPUT. RESISTOR. Y C N. E U. 16.9k. 20k. E FR. 10kHz. 40.2k. 100k. 100. 1000. COS (pF). INPUT RESISTOR. pm p. ITY. R A E
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Data Sheet AD650
If the approximate amount of noise that appears on CINT is known
1MHz
(VNOISE), then the value of CINT can be checked using the following inequality: t 1 10 3 A
LE
OS
A
C (8)
C
INT V V 3 V
S 100kHz
S NOISE
L- L INPUT FU RESISTOR
For example, consider an application calling for a maximum
Y C N
frequency of 75 kHz, a 0 V to 1 V signal range, and supply
E U 16.9k Q 20k
voltages of only ±9 V. The component selection guide of Figure 9
E FR
is used to select 2.0 kΩ for R
10kHz 40.2k
IN and 1000 pF for COS. This results in a one-shot time period of approximately 7 μs. Substituting 08 0
100k
7- 75 kHz into Equation 7 yields a value of 1300 pF for C 79 INT. When 00 the input signal is near zero, 1 mA flows through the integration
50 100 1000
capacitor to the switched current sink during the reset phase,
COS (pF)
causing the voltage across CINT to increase by approximately 5.5 V. Figure 9. Full-Scale Frequency vs. COS Because the integrator output stage requires approximately 3 V headroom for proper operation, only 0.5 V margin remains for
INPUT RESISTOR 1000
integrating extraneous noise on the signal line. A negative noise
) 16.9k
pulse at this time could saturate the integrator, causing an error
pm p 20k
in signal integration. Increasing C
(
INT to 1500 pF or 2000 pF
ITY
provides much more noise margin, thereby eliminating this
R A E 40.2k
potential trouble spot.
IN L N 100 O 100k N L A IC P TY 20
9 00 7- 79 00
50 100 1000 ONE SHOT CAPACITOR COS (pF)
Figure 10. Typical Nonlinearity vs. COS Rev. E | Page 9 of 20 Document Outline Features Functional Block Diagram Product Description Product Highlights Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Circuit Operation Unipolar Configuration One-Shot Timing Component Selection Bipolar V/F Unipolar V/F, Negative Input Voltage F/V Conversion High Frequency Operation Decoupling and Grounding Temperature Coefficients Nonlinearity Specification PSRR Other Circuit Considerations Applications Differential Voltage-to-Frequency Conversion Autozero Circuit Phase-Locked Loop F/V Conversion Outline Dimensions Ordering Guide
Data Sheet AD650
If the approximate amount of noise that appears on CINT is known
1MHz
(VNOISE), then the value of CINT can be checked using the following inequality: t 1 10 3 A
LE
OS
A
C (8)
C
INT V V 3 V
S 100kHz
S NOISE
L- L INPUT FU RESISTOR
For example, consider an application calling for a maximum
Y C N
frequency of 75 kHz, a 0 V to 1 V signal range, and supply
E U 16.9k Q 20k
voltages of only ±9 V. The component selection guide of Figure 9
E FR
is used to select 2.0 kΩ for R
10kHz 40.2k
IN and 1000 pF for COS. This results in a one-shot time period of approximately 7 μs. Substituting 08 0
100k
7- 75 kHz into Equation 7 yields a value of 1300 pF for C 79 INT. When 00 the input signal is near zero, 1 mA flows through the integration
50 100 1000
capacitor to the switched current sink during the reset phase,
COS (pF)
causing the voltage across CINT to increase by approximately 5.5 V. Figure 9. Full-Scale Frequency vs. COS Because the integrator output stage requires approximately 3 V headroom for proper operation, only 0.5 V margin remains for
INPUT RESISTOR 1000
integrating extraneous noise on the signal line. A negative noise
) 16.9k
pulse at this time could saturate the integrator, causing an error
pm p 20k
in signal integration. Increasing C
(
INT to 1500 pF or 2000 pF
ITY
provides much more noise margin, thereby eliminating this
R A E 40.2k
potential trouble spot.
IN L N 100 O 100k N L A IC P TY 20
9 00 7- 79 00
50 100 1000 ONE SHOT CAPACITOR COS (pF)
Figure 10. Typical Nonlinearity vs. COS Rev. E | Page 9 of 20 Document Outline Features Functional Block Diagram Product Description Product Highlights Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Circuit Operation Unipolar Configuration One-Shot Timing Component Selection Bipolar V/F Unipolar V/F, Negative Input Voltage F/V Conversion High Frequency Operation Decoupling and Grounding Temperature Coefficients Nonlinearity Specification PSRR Other Circuit Considerations Applications Differential Voltage-to-Frequency Conversion Autozero Circuit Phase-Locked Loop F/V Conversion Outline Dimensions Ordering Guide