Datasheet AD650 (Analog Devices) - 8

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Data Sheet AD650 CIRCUIT OPERATION UNIPOLAR CONFIGURATION C COS INT INTEGRATOR
The AD650 is a charge balance voltage-to-frequency converter.
IIN
In the connection diagram shown in Figure 4, or the block
FREQUENCY COMPARATOR R OUTPUT IN
diagram of Figure 5, the input signal is converted into an
+ ONE V
equivalent current by the input resistance R
IN SHOT
IN. This current is
–
exactly balanced by an internal feedback current delivered in
S1 –0.6V
short, timed bursts from the switched 1 mA internal current source. These bursts of current can be thought of as precisely
AD650 1mA ± 20% t t
defined packets of charge. The required number of charge
OS
4 0 0 packets, each producing one pulse of the output transistor, 7-
–V
79
S
00 depends upon the amplitude of the input signal. Because the Figure 5. Block Diagram number of charge packets delivered per unit time is dependent on the input signal amplitude, a linear voltage-to-frequency
CINT
transformation is accomplished. The frequency output is
IIN 1mA – IIN
furnished via an open collector transistor.
+ V R IN IN –
A more rigorous analysis demonstrates how the charge balance
1mA
voltage-to-frequency conversion takes place.
S1
A block diagram of the device arranged as a V-to-F converter is
1mA
shown in Figure 5. The unit is comprised of an input integrator, 5 00 a current source and steering switch, a comparator, and a one 7-
–V
79
S
00 shot. When the output of the one shot is low, the current Figure 6. Reset Mode steering switch S1 diverts all the current to the output of the op amp; this is called the integration period. When the one shot
C I INT IN
has been triggered and its output is high, the switch S
IIN
1 diverts
1mA – IIN
all the current to the summing junction of the op amp; this is
+ V R IN IN
called the reset period. The two different states are shown in
– 1mA
Figure 6 and Figure 7 along with the various branch currents. It should be noted that the output current from the op amp is the
S1
same for either state, thus minimizing transients.
1mA
6 00 7-
–V
79
S
00
AD650
Figure 7. Integrate Mode
CINT 1 14 INPUT 20kΩ OP OFFSET AMP TRIM RESET INTEGRATE 2 13 RIN 250kΩ V 3 12 +15V IN R3 R1 0.1µF S1 4 11 S ANALOG T L –V 1mA –0.6V GROUND S 1µF VO –15V 5 OUT 10 V ∆V –V LOGIC S 0.1µF IN FREQ ONE 6 OUT SHOT 9 R2 COMP C DIGITAL OS GROUND
003
7 8 FOUT t
0797- 0 Figure 4. Connection Diagram for V/F Conversion, Positive Input Voltage 7
–0.6
-00 97
tOS T1
07 0 Figure 8. Voltage Across CINT Rev. E | Page 7 of 20 Document Outline Features Functional Block Diagram Product Description Product Highlights Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Circuit Operation Unipolar Configuration One-Shot Timing Component Selection Bipolar V/F Unipolar V/F, Negative Input Voltage F/V Conversion High Frequency Operation Decoupling and Grounding Temperature Coefficients Nonlinearity Specification PSRR Other Circuit Considerations Applications Differential Voltage-to-Frequency Conversion Autozero Circuit Phase-Locked Loop F/V Conversion Outline Dimensions Ordering Guide