Datasheet AD652 (Analog Devices) - 7

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AD652 THEORY OF OPERATION F
A synchronous VFC is similar to other voltage-to-frequency
RE
converters in that an integrator is used to perform a charge-
S
balance of the input signal with an internal reference current.
NC +V NC COMP NC 3 2 1 20 19
However, rather than using a one-shot as the primary timing
AD652
element, which requires a high quality and low drift capacitor, a
SYNCHRONOUS 5V VOLTAGE-TO-FREQUENCY REFERENCE
synchronous voltage-to-frequency converter (SVFC) uses an
CONVERTER OP AMP OUT 4 18 COMP "+"
external clock. This allows the designer to determine the system stability and drift based upon the external clock selected. A
OP AMP "–" 5 17 COMP "–"
crystal oscillator may also be used if desired.
Q "D" OP AMP "+" 6 16 ANALOG GND
The SVFC architecture provides other system advantages
FLOP AND D 10k
Ω besides low drift. If the output frequency is measured by
Q CK 5V INPUT 7 15 DIGITAL GND
counting pulses gated to a signal that is derived from the clock,
10k
Ω
1mA ONE
the clock stability is unimportant and the device simply
10V INPUT 16k
Ω
SHOT 8 14 FREQ OUT
performs as a voltage-controlled frequency divider, producing a
4k
Ω high resolution A/D. If a large number of inputs must be
9 10 11 12 13
monitored simultaneously in a system, the controlled timing
T S NC = NO CONNECT OS –V
relationship between the frequency output pulses and the user-
PU C INPUT CLOCK
supplied clock greatly simplifies this signal acquisition. Also, if
8V INPUT OPTIONAL 10V IN
00798-003 the clock signal is provided by a VFC, the output frequency of Figure 3. PLCC Pin Configuration the SVFC is proportional to the product of the two input voltages. Therefore, multiplication and A-to-D conversion on Figure 4 shows the typical up-and-down ramp integrator output two signals are performed simultaneously. of a charge-balance VFC. After the integrator output has crossed the comparator threshold and the output of the AND
AD652
gate has gone high, nothing happens until a negative edge of the
SYNCHRONOUS VOLTAGE-TO-
clock comes along to transfer the information to the output of
5V +VS 1 FREQUENCY 16 COMP REF REFERENCE CONVERTER
the D FLOP. At this point, the clock level is low, so the latch does
TRIM 2 15 COMP "+"
not change state. When the clock returns high, the latch output
TRIM 3 14 COMP "–"
goes high and drives the switch to reset the integrator; at the
OP AMP OUT 4 13 ANALOG GND
same time, the latch drives the AND gate to a low output state.
OP AMP "–" 5 12 DIGITAL GND ONE
On the very next negative edge of the clock, the low output state
SHOT OP AMP "+" 6 11 FREQ OUT
of the AND gate is transferred to the output of the D FLOP.
20k
Ω
10 VOLT INPUT 7 10 CLOCK INPUT 1mA
When the clock returns high, the latch output goes low and
Q CK –VS 8 9 COS
drives the switch back into the Integrate mode. At the same
AND D "D" Q FLOP
time, the latch drives the AND gate to a mode where it 00798-002 truthfully relays the information presented to it by the Figure 2. CERDIP Pin Configuration comparator. The pinouts of the AD652 SVFC are shown in Figure 2 and Because the reset pulses applied to the integrator are exactly one Figure 3. A block diagram of the device configured as an SVFC, clock period long, the only place where drift can occur is in a along with various system waveforms, is shown in Figure 4. variation of the symmetry of the switching speed with temperature. Since each reset pulse is identical, the AD652 SVFC produces a very linear voltage-to-frequency transfer relation. Also, because all reset pulses are gated by the clock, there are no problems with dielectric absorption causing the duration of a reset pulse to be influenced by the length of time since the last reset. Rev. C | Page 6 of 28 Document Outline FEATURES PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION DEFINITIONS OF SPECIFICATIONS THEORY OF OPERATION OVERRANGE SVFC CONNECTION FOR DUAL SUPPLY, POSITIVE INPUT VOLTAGES SVFC CONNECTIONS FOR NEGATIVE INPUT VOLTAGES SVFC CONNECTION FOR BIPOLAR INPUT VOLTAGES PLCC CONNECTIONS GAIN AND OFFSET CALIBRATION GAIN PERFORMANCE REFERENCE NOISE DIGITAL INTERFACING CONSIDERATIONS COMPONENT SELECTION DIGITAL GROUND SINGLE-SUPPLY OPERATION FREQUENCY-TO-VOLTAGE CONVERTER DECOUPLING AND GROUNDING FREQUENCY OUTPUT MULTIPLIER SINGLE-LINE MULTIPLEXED DATA TRANSMISSION Multiplexer Transmitter SVFC Demultiplexer Analog Signal Reconstruction ISOLATED FRONT END A-TO-D CONVERSION DELTA MODULATOR BRIDGE TRANSDUCER INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE