Datasheet AD652 (Analog Devices) - 9

link to page 9 link to page 9
AD652
Another way to view this is that the output is a frequency of The result of this synchronism is that the rate at which data may approximately one-quarter of the clock that has been phase be extracted from the series bit stream produced by the SVFC is modulated. A constant frequency can be thought of as limited. The output pulses are typically counted during a fixed accumulating phase linearly with time at a rate equal to 2πf gate interval and the result is interpreted as an average radians per second. Therefore, the average output frequency, frequency. The resolution of such a measurement is determined which is slightly in excess of a quarter of the clock, requires by the clock frequency and the gate time. For example, if the phase accumulation at a certain rate. However, since the SVFC clock frequency is 4 MHz and the gate time is 4.096 ms, a is running at exactly one-quarter of the clock, it does not maximum count of 8,192 is produced by a full-scale frequency accumulate enough phase (see Figure 7). When the difference of 2 MHz. Thus, the resolution is 13 bits. between the required phase (average frequency) and the actual
OVERRANGE
phase equals 2π, a step-in phase is taken where the deficit is made up instantaneously. The output frequency is then a steady Since each reset pulse is only one clock period in length, the carrier that has been phase modulated by a sawtooth signal (see full-scale output frequency is equal to one-half the clock Figure 7). The period of the sawtooth phase modulation is the frequency. At full scale, the current steering switch spends half time required to accumulate a 2π difference in phase between of the time on the summing junction; thus, an input current of the required average frequency and one quarter of the clock 0.5 mA can be balanced. In the case of an overrange, the output frequency. The sawtooth phase modulation amplitude is 2π. of the integrator op amp drifts in the negative direction and the output of the comparator remains high. The logic circuits simply settle into a divide-by-two of the clock state.
PHASE 2
π
EXPECTED PHASE 2
π
ACTUAL PHASE TIME
φ
MOD (t) TIME 2
π
V
×
OUT (t) = COS (2
π ×
fAVE t +
φ
MOD (t)) AVERAGE PHASE CARRIER FREQUENCY MODULATION
00798-007 Figure 7. Phase Modulation Rev. C | Page 8 of 28 Document Outline FEATURES PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION DEFINITIONS OF SPECIFICATIONS THEORY OF OPERATION OVERRANGE SVFC CONNECTION FOR DUAL SUPPLY, POSITIVE INPUT VOLTAGES SVFC CONNECTIONS FOR NEGATIVE INPUT VOLTAGES SVFC CONNECTION FOR BIPOLAR INPUT VOLTAGES PLCC CONNECTIONS GAIN AND OFFSET CALIBRATION GAIN PERFORMANCE REFERENCE NOISE DIGITAL INTERFACING CONSIDERATIONS COMPONENT SELECTION DIGITAL GROUND SINGLE-SUPPLY OPERATION FREQUENCY-TO-VOLTAGE CONVERTER DECOUPLING AND GROUNDING FREQUENCY OUTPUT MULTIPLIER SINGLE-LINE MULTIPLEXED DATA TRANSMISSION Multiplexer Transmitter SVFC Demultiplexer Analog Signal Reconstruction ISOLATED FRONT END A-TO-D CONVERSION DELTA MODULATOR BRIDGE TRANSDUCER INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE