Datasheet ADXL180 (Analog Devices) - 7

link to page 6 link to page 3 link to page 39 link to page 39 link to page 39 link to page 3 link to page 19 link to page 7 link to page 6
ADXL180 Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
ASYNCHRONOUS MODE TIMING2 Message Transmission Period Phase 2, Mode 0 tPM0 456 μs ADIFX compatible All Other Phases and Modes tP 228 μs Initialization State (Phase 1) tI 100 ms Device Data State (Phase 2) ms Mode 0 tDD0 4.10 ms Mode 1 tDD1 109 ms Mode 2 tDD2 109 ms Mode 3 tDD3 117 ms Self-Test State (Phase 3) Self-Test Time3 tST 394 ms See Figure 28 Self-Test Interval tSTI 21.9 ms See Figure 28 Self-Test Cycle tSTC 65.7 ms See Figure 28 Auto-Zero Initialization State tAZ 14.94 sec (Phase 4) SYNCHRONOUS MODE TIMING4 Message Transmission Period tPS N/A Determined by sync pulse, See Figure 14, minimum tPS = tSPD + tSTD + tM + tB Initialization State1 (Phase 1) tI 100 ms Device Data State (Phase 2) ms Mode 0 tDD0s 9 × tPS ms Mode 1 tDD1s 480 × tPS ms Mode 2 tDD2s 480 × tPS ms Mode 3 tDD3s 512 × tPS ms Self-Test State (Phase 3) Self-Test Time3 tSTS 1728 × tPS ms Self-Test Interval tSTIS 96 × tPS ms Self-Test Cycle tSTCS 288 × tPS ms Auto-Zero Initialization State tAZs 65,535 × tPS sec (Phase 4) CLOCK Period2 tCLK 1.05 1.0 0.95 μs fCLK = 1/tCLK PSRR <1 LSB 8-bit LSB; test conditions: VBP − VBN = 7.00 V, VAC = 500 mV p-p, 100 kHz to 1.1 MHz POWER SUPPLY HOLDUP TIME 500 ns @ IBUS = ISIG THERMAL RESISTANCE, JUNCTION θJC 30 °C/W TO CASE 1 All parameters are specified using the application circuit shown in Figure 6. CB = 10 nF, CVDD = 100 nF. 2 All timing is driven from the on-chip master clock. 3 tST and tSTS are the times for six self-test cycles. This is the maximum number of cycles in the internal self-test mode. 4 Transmission timing is defined by the internal system clock in asynchronous mode and by the synchronization pulse period in synchronous mode. Rev. A | Page 6 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION OVERVIEW ACCELERATION SENSOR SIGNAL PROCESSING DIGITAL COMMUNICATIONS STATE MACHINE 2-WIRE CURRENT MODULATED INTERFACE SYNCHRONOUS OPERATION AND DUAL DEVICE BUS PROGRAMMED MEMORY AND CONFIGURABILITY Factory-Programmed Serial Number and Manufacturer Information User-Programmable Data Register User-Programmed Configuration Physical Layer (ISO Layer 1) Data Link Layer (ISO Layer 2) Application Layer (ISO Layer 7) PHYSICAL INTERFACE APPLICATION CIRCUIT CURRENT MODULATION MANCHESTER DATA ENCODING OPERATION AT LOW VBP OR LOW VDD OPERATION AT HIGH VDD COMMUNICATIONS TIMING AND BUS TOPOLOGIES DATA TRANSMISSION ASYNCHRONOUS COMMUNICATION Asynchronous Single Device Point-to-Point Topology SYNCHRONOUS COMMUNICATION Configuring the ADXL180 for Synchronous Operation Synchronization Pulse Detection Bus Discharge Enable Synchronous Single Device Point-to-Point Topology SYNCHRONOUS COMMUNICATION MODE—DUAL DEVICE Configuring Synchronous Operation Delay Selection Fixed Delay Mode Autodelay Mode Dual Device Synchronous Parallel Topology Dual Device Synchronous Series Topology DATA FRAME DEFINITION DATA FRAME TRANSMISSION FORMAT DATA FRAME CONFIGURATION OPTIONS ACCELERATION DATA CODING STATE VECTOR CODING STATE VECTOR DESCRIPTIONS TRANSMISSION ERROR DETECTION OPTIONS CRC Encoding Parity Encoding APPLICATION LAYER: COMMUNICATION PROTOCOL STATE MACHINE ADXL180 STATE MACHINE PHASE 1: POWER-ON-RESET INITIALIZATION PHASE 2: DEVICE DATA TRANSMISSION Overview Influence of MD on Data Range Device Data Mapping in Phase 2 PHASE 2: MODE DESCRIPTION Mode 0 Asynchronous Mode Synchronous Mode Mode 1 Mode 2 Device Data User Bits and User Register (UREG) 10-Bit Data and Mode 2 Mode 3 Device Data User Register (UREG) Use with State Vector Enabled Illegal Configuration: Mode 3 and 8-Bit Data PHASE 3: SELF-TEST DIAGNOSTIC Concept of Self-Test Internal and External Self-Test Option External Self-Test Internal Self-Test Influence of MD Selections On Transmitted Self-Test Data PHASE 4: AUTO-ZERO INITIALIZATION Fast Auto-Zero Mode Error Reporting PHASE 5: NORMAL OPERATION Slow Auto-Zero Error Reporting SIGNAL RANGE AND FILTERING TRANSFER FUNCTION OVERVIEW RANGE THREE-POLE BESSEL FILTER AUTO-ZERO OPERATION Offset Drift Monitoring ERROR DETECTION OVERVIEW PARITY ERROR DUE TO COMMUNICATIONS PROTOCOL CONFIGURATION BIT ERROR SELF-TEST ERROR OFFSET ERROR/OFFSET DRIFT MONITORING VOLTAGE REGULATOR MONITOR RESET OPERATION TEST AND DIAGNOSTIC TOOLS VSCI SIGNAL CHAIN INPUT TEST PIN VSCO ANALOG SIGNAL CHAIN OUTPUT TEST PIN CONFIGURATION SPECIFICATION OVERVIEW CONFIGURATION MODE TRANSMIT COMMUNICATIONS PROTOCOL CONFIGURATION MODE COMMAND (RECEIVE) COMMUNICATIONS PROTOCOL CONFIGURATION MODE COMMUNICATIONS HANDSHAKING CONFIGURATION AND USER DATA REGISTERS CONFIGURATION MODE EXIT SERIAL NUMBER AND MANUFACTURER IDENTIFICATION DATA REGISTERS PROGRAMMING THE CONFIGURATION AND USER DATA REGISTERS OTP PROGRAMMING CONDITIONS AND CONSIDERATIONS CONFIGURATION/USER REGISTER OTP PARITY CONFIGURATION MODE ERROR REPORTING CONFIGURATION REGISTER REFERENCE UD[7:0] USER DATA BITS UD8 CONFIGURATION BIT BDE SCOE FDLY ADME STI FC[1:0] RG[2:0] MD[1:0] SYEN AZE ERC DAT SVD CUPAR AND CUPRG AXIS OF SENSITIVITY BRANDING OUTLINE DIMENSIONS ORDERING GUIDE