Datasheet ADXL180 (Analog Devices)
Hersteller | Analog Devices |
Beschreibung | Configurable, High-g, iMEMS® Accelerometer |
Seiten / Seite | 61 / 1 — Configurable, High g,. MEMS Accelerometer. ADXL180. FEATURES. GENERAL … |
Revision | B |
Dateiformat / Größe | PDF / 630 Kb |
Dokumentensprache | Englisch |
Configurable, High g,. MEMS Accelerometer. ADXL180. FEATURES. GENERAL DESCRIPTION. Wide sensor range: 50 g. to 500 g
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Configurable, High g, i MEMS Accelerometer ADXL180 FEATURES GENERAL DESCRIPTION Wide sensor range: 50 g to 500 g
The ADXL180 iMEMS® accelerometer is a configurable, single
Adjustable filter bandwidth: 100 Hz to 800 Hz
axis, integrated satellite sensor that enables low cost solutions
Configurable communication protocol
for front and side impact airbag applications. Acceleration data
2-wire, current mode bus interface
is sent to the control module via a digital 2-wire current loop
Selectable sensor data resolution: 8 bit or 10 bit
interface bus. The communication protocol is programmable for
Continuous auto-zero
compatibility with various automotive interface bus standards.
Fully differential sensor and interface circuitry
The sensor g range is configurable to provide full-scale ranges
High resistance to EMI/RFI
from ±50 g to ±500 g. The sensor signal third-order, low-pass
Sensor self-test
Bessel filter bandwidth is configurable at 100 Hz, 200 Hz,
5.0 V to 14.5 V operation
400 Hz, and 800 Hz.
8 bits of user-defined OTP memory 32-bit electronic serial number
The 10-bit analog-to-digital converter (ADC) allows either 8-bit
Dual device per bus option
or 10-bit acceleration data to be transmitted to the control module. Each part has a unique electronic serial number. The device is
APPLICATIONS
rated for operation from −40°C to +125°C and is available in a
Crash sensing
5 mm × 5 mm LFCSP package.
FUNCTIONAL BLOCK DIAGRAM ADXL180 VBP SERIAL SERIAL PORT COMM NUMBER OSCILLATOR/ INTERFACE V OTP BC TIMING V V/Q FUSE TRIMS SCI V GENERATOR BN ROM CONFIGURATION SYNC DATA DETECT PROGRAM INTERFACE 3-POLE 10- DIFF AUTO- MOD DEMOD BESSEL BIT SENSOR ZERO STATE VOLTAGE V AMP DD FILTER ADC MACHINE REGULATOR SUPPLY MONITOR VCM SELF- REF TEST
01 0 4- 54
V V CM SCO
07 Figure 1.
Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION OVERVIEW ACCELERATION SENSOR SIGNAL PROCESSING DIGITAL COMMUNICATIONS STATE MACHINE 2-WIRE CURRENT MODULATED INTERFACE SYNCHRONOUS OPERATION AND DUAL DEVICE BUS PROGRAMMED MEMORY AND CONFIGURABILITY Factory-Programmed Serial Number and Manufacturer Information User-Programmable Data Register User-Programmed Configuration Physical Layer (ISO Layer 1) Data Link Layer (ISO Layer 2) Application Layer (ISO Layer 7) PHYSICAL INTERFACE APPLICATION CIRCUIT CURRENT MODULATION MANCHESTER DATA ENCODING OPERATION AT LOW VBP OR LOW VDD OPERATION AT HIGH VDD COMMUNICATIONS TIMING AND BUS TOPOLOGIES DATA TRANSMISSION ASYNCHRONOUS COMMUNICATION Asynchronous Single Device Point-to-Point Topology SYNCHRONOUS COMMUNICATION Configuring the ADXL180 for Synchronous Operation Synchronization Pulse Detection Bus Discharge Enable Synchronous Single Device Point-to-Point Topology SYNCHRONOUS COMMUNICATION MODE—DUAL DEVICE Configuring Synchronous Operation Delay Selection Fixed Delay Mode Autodelay Mode Dual Device Synchronous Parallel Topology Dual Device Synchronous Series Topology DATA FRAME DEFINITION DATA FRAME TRANSMISSION FORMAT DATA FRAME CONFIGURATION OPTIONS ACCELERATION DATA CODING STATE VECTOR CODING STATE VECTOR DESCRIPTIONS TRANSMISSION ERROR DETECTION OPTIONS CRC Encoding Parity Encoding APPLICATION LAYER: COMMUNICATION PROTOCOL STATE MACHINE ADXL180 STATE MACHINE PHASE 1: POWER-ON-RESET INITIALIZATION PHASE 2: DEVICE DATA TRANSMISSION Overview Influence of MD on Data Range Device Data Mapping in Phase 2 PHASE 2: MODE DESCRIPTION Mode 0 Asynchronous Mode Synchronous Mode Mode 1 Mode 2 Device Data User Bits and User Register (UREG) 10-Bit Data and Mode 2 Mode 3 Device Data User Register (UREG) Use with State Vector Enabled Illegal Configuration: Mode 3 and 8-Bit Data PHASE 3: SELF-TEST DIAGNOSTIC Concept of Self-Test Internal and External Self-Test Option External Self-Test Internal Self-Test Influence of MD Selections On Transmitted Self-Test Data PHASE 4: AUTO-ZERO INITIALIZATION Fast Auto-Zero Mode Error Reporting PHASE 5: NORMAL OPERATION Slow Auto-Zero Error Reporting SIGNAL RANGE AND FILTERING TRANSFER FUNCTION OVERVIEW RANGE THREE-POLE BESSEL FILTER AUTO-ZERO OPERATION Offset Drift Monitoring ERROR DETECTION OVERVIEW PARITY ERROR DUE TO COMMUNICATIONS PROTOCOL CONFIGURATION BIT ERROR SELF-TEST ERROR OFFSET ERROR/OFFSET DRIFT MONITORING VOLTAGE REGULATOR MONITOR RESET OPERATION TEST AND DIAGNOSTIC TOOLS VSCI SIGNAL CHAIN INPUT TEST PIN VSCO ANALOG SIGNAL CHAIN OUTPUT TEST PIN CONFIGURATION SPECIFICATION OVERVIEW CONFIGURATION MODE TRANSMIT COMMUNICATIONS PROTOCOL CONFIGURATION MODE COMMAND (RECEIVE) COMMUNICATIONS PROTOCOL CONFIGURATION MODE COMMUNICATIONS HANDSHAKING CONFIGURATION AND USER DATA REGISTERS CONFIGURATION MODE EXIT SERIAL NUMBER AND MANUFACTURER IDENTIFICATION DATA REGISTERS PROGRAMMING THE CONFIGURATION AND USER DATA REGISTERS OTP PROGRAMMING CONDITIONS AND CONSIDERATIONS CONFIGURATION/USER REGISTER OTP PARITY CONFIGURATION MODE ERROR REPORTING CONFIGURATION REGISTER REFERENCE UD[7:0] USER DATA BITS UD8 CONFIGURATION BIT BDE SCOE FDLY ADME STI FC[1:0] RG[2:0] MD[1:0] SYEN AZE ERC DAT SVD CUPAR AND CUPRG AXIS OF SENSITIVITY BRANDING OUTLINE DIMENSIONS ORDERING GUIDE