Datasheet ADXL362 (Analog Devices) - 9

Data Sheet ADXL362 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ND S G NC V 16 15 14 VDDI/O 1 13 GND NC 2 12 GND ADXL362 RESERVED 3 11 INT1 TOP VIEW (Not to Scale) SCLK 4 10 RESERVED RESERVED 5 9 INT2 6 7 8 SI SO CS MO MI NOTES 1. NC = NO CONNECT. THIS PIN IS NOT
004
INTERNALLY CONNECTED.
10776- Figure 4. Pin Configuration (Top View)
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 VDD I/O Supply Voltage for Digital I/O. 2 NC No Connect. Not internally connected. 3 Reserved Reserved. Can be left unconnected or connected to GND. 4 SCLK SPI Communications Clock. 5 Reserved Reserved. Can be left unconnected or connected to GND. 6 MOSI Master Output, Slave Input. SPI serial data input. 7 MISO Master Input, Slave Output. SPI serial data output. 8 CS SPI Chip Select, Active Low. Must be low during SPI communications. 9 INT2 Interrupt 2 Output. INT2 also serves as an input for synchronized sampling. 10 Reserved Reserved. Can be left unconnected, or connected to GND. 11 INT1 Interrupt 1 Output. INT1 also serves as an input for external clocking. 12 GND Ground. This pin must be grounded. 13 GND Ground. This pin must be grounded. 14 VS Supply Voltage. 15 NC No Connect. Not internally connected. 16 GND Ground. This pin must be grounded. Rev. E | Page 7 of 43 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE PACKAGE INFORMATION RECOMMENDED SOLDERING PROFILE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION MECHANICAL DEVICE OPERATION OPERATING MODES Measurement Mode Wake-Up Mode Standby SELECTABLE MEASUREMENT RANGES SELECTABLE OUTPUT DATA RATES Antialiasing POWER/NOISE TRADEOFF POWER SAVINGS FEATURES ULTRALOW POWER CONSUMPTION IN ALL MODES MOTION DETECTION Activity Detection Referenced and Absolute Configurations Fewer False Positives Inactivity Detection Linking Activity and Inactivity Detection Default Mode Linked Mode Loop Mode Autosleep Using the AWAKE Bit FIFO System Level Power Savings Data Recording/Event Context COMMUNICATIONS SPI Instructions Bus Keepers MSB Registers ADDITIONAL FEATURES FREE FALL DETECTION EXTERNAL CLOCK SYNCHRONIZED DATA SAMPLING SELF TEST USER REGISTER PROTECTION TEMPERATURE SENSOR SERIAL COMMUNICATIONS SPI COMMANDS Read and Write Register Commands Read FIFO Command MULTIBYTE TRANSFERS Register Read/Write Auto-Increment INVALID ADDRESSES AND ADDRESS FOLDING LATENCY RESTRICTIONS INVALID COMMANDS REGISTER MAP REGISTER DETAILS DEVICE ID REGISTER DEVICE ID: 0x1D REGISTER PART ID: 0xF2 REGISTER SILICON REVISION ID REGISTER X-AXIS DATA (8 MSB) REGISTER Y-AXIS DATA (8 MSB) REGISTER Z-AXIS DATA (8 MSB) REGISTER STATUS REGISTER FIFO ENTRIES REGISTERS X-AXIS DATA REGISTERS Y-AXIS DATA REGISTERS Z-AXIS DATA REGISTERS TEMPERATURE DATA REGISTERS SOFT RESET REGISTER ACTIVITY THRESHOLD REGISTERS ACTIVITY TIME REGISTER INACTIVITY THRESHOLD REGISTERS INACTIVITY TIME REGISTERS ACTIVITY/INACTIVITY CONTROL REGISTER FIFO CONTROL REGISTER FIFO SAMPLES REGISTER INT1/INT2 FUNCTION MAP REGISTERS FILTER CONTROL REGISTER POWER CONTROL REGISTER SELF TEST REGISTER APPLICATIONS INFORMATION APPLICATION EXAMPLES Device Configuration Autonomous Motion Switch Start-up Routine Using External Timing Triggers Example: Implementing Free Fall Detection Start-up Routine POWER Power Supply Decoupling Power Supply Requirements FIFO MODES FIFO Disabled Oldest Saved Mode Stream Mode Triggered Mode FIFO Configuration FIFO Interrupts Retrieving Data from FIFO INTERRUPTS Interrupt Pins Alternate Functions of Interrupt Pins Activity and Inactivity Interrupts Data Ready Interrupt Using FIFO Interrupts FIFO Watermark FIFO Ready Overrun USING SYNCHRONIZED DATA SAMPLING USING AN EXTERNAL CLOCK USING SELF TEST OPERATION AT VOLTAGES OTHER THAN 2.0 V MECHANICAL CONSIDERATIONS FOR MOUNTING AXES OF ACCELERATION SENSITIVITY LAYOUT AND DESIGN RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE