Datasheet LTC4309 (Analog Devices) - 8

LTC4309
OPERATION Start-Up
All four rise time accelerators can be disabled by connect- When the LTC4309 fi rst receives power on its V ing ACC to VCC. To activate the rise time accelerators on CC pin, either during power up or live insertion, it starts in an under only SDAOUT and SCLOUT, connect both ACC and VCC2 voltage lockout (UVLO) state, ignoring any activity on the to ground. The rise time accelerators are also internally SDA or SCL pins until V disabled until the sequence of events described in the CC rises above 2V. This ensures the LTC4309 does not try to function until enough supply start-up section have been completed, as well as during voltage is present. automatic clocking and stop bit generation for a bus stuck low recovery event. During this time, the 1V precharge circuitry is actively forcing 1V through 100k nominal resistors to the SDA
Connection Circuitry
and SCL pins. Because the I/O card is being plugged Once the connection circuitry is activated, the functionality into a live backplane, the voltage on the backplane SDA of the input and output bus of the respective SDA or SCL and SCL busses may be anywhere between 0V and VCC. pins are identical. A low forced on either output or input Precharging the SCL and SDA pins to 1V minimizes the pin at any time results in both pin voltages forced low. worst-case voltage differential these pins will see at the The LTC4309 is tolerant of I2C bus DC logic low voltages moment of contact, therefore minimizing the amount of up to the V disturbance caused by the I/O card. IL specifi cation of 0.3 • VCC. When the LTC4309 senses a rising edge on the bus, with Once the LTC4309 exits from UVLO, it monitors both the a slew rate greater than 0.8V/μs, the internal pull-down input and output pins for either a stop bit or a bus idle device for the respective bus is deactivated at bus volt- condition to indicate the completion of data transactions. ages as low as 0.48V. This methodology maximizes the When both sides are idle or one side has a stop bit while effectiveness of the rise time accelerator circuitry and the other is idle, the connection circuitry is activated, maintains compatibility with other devices in the LTC4300 joining the SDA and SCL busses on the input side with bus buffer family. Care must be taken to ensure devices those on the output side. participating in clock stretching or arbitration are capable
Rise Time Accelerators
of forcing logic low voltages below 0.48V at the LTC4309’s Once connection has been established if ACC is connected SDA and SCL pins. to ground and VCC2 is powered from a supply voltage greater A high occurs when all devices on the input and output than or equal to 1.8V, the rise time accelerator circuits on pins release high. These important features ensures the all four SDA and SCL pins are enabled. During positive bus I2C specifi cation protocols such as clock stretching, clock transitions of at least 0.8V/μs, the rise time accelerators synchronization, arbitration, and acknowledge function provide strong, slew-limited pull-up currents to force the seamlessly in all cases as specifi ed, regardless of how the bus voltage to rise at a rate of 100V/μs. Enabling the rise devices in the system are connected to the LTC4309. time accelerators allows users to choose larger bus pull- Another key feature provided by the connection circuitry up resistors, reducing power consumption and improving is input and output bus capacitance isolation through logic low noise margins, or design with bus capacitances bidirectional buffering. Because of this isolation, the beyond those specifi ed in the I2C specifi cations. waveforms on the input busses look slightly different than To ensure the rise time accelerators are properly activated the corresponding output bus waveforms, as described when the rise time accelerators are enabled, users should below. choose bus pull-up resistors that guarantee the bus will rise on its own at a rate of at least 0.8V/μs. See the Ap-
Input to Output Offset Voltage
plication Information section for determining the correct When a logic low voltage is driven on any of the LTC4309’s pull-up resistor size. data or clock pins, the LTC4309 regulates the voltage on the other side of the device to a slightly higher voltage, 4309fa 8