Datasheet LTC4309 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| Seiten / Seite | 16 / 9 — OPERATION. Figure 2. Input-Output Rising Edge Waveforms. Figure 3. … |
| Dateiformat / Größe | PDF / 205 Kb |
| Dokumentensprache | Englisch |
OPERATION. Figure 2. Input-Output Rising Edge Waveforms. Figure 3. Input-Output Falling Edge Waveforms. Bus Stuck Low Timeout
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LTC4309
OPERATION
OUTPUT SIDE INPUT SIDE INPUT SIDE OUTPUT SIDE 50pF 150pF 150pF 50pF 1V/DIV 1V/DIV 1V/DIV 1V/DIV 200ns/DIV 4307 F01 200ns/DIV 4307 F02
Figure 2. Input-Output Rising Edge Waveforms Figure 3. Input-Output Falling Edge Waveforms
typically 60mV. This offset is nearly independent of pull-up
Bus Stuck Low Timeout
current. (See Typical Performance curves.) When SDAOUT or SCLOUT is low, an internal timer is started. The timer is only reset by the respective pin
Propagation Delays
going high. If the bus stuck low does not go high within During a rising edge, the rise time on each side is de- 30ms (typical), the FAULT pin pulls low indicating a bus termined by the bus pull-up resistor and the equivalent stuck low condition. If DISCEN is connected to VCC, the capacitance on the line. If the pull-up resistors are the connection circuitry is disabled, breaking the connection same, a difference in rise time occurs which is directly between the respective input and output pins. In addition, proportional to the difference in capacitance between the after at least 40μs, up to 16 clock pulses at 8.5kHz (typi- two sides. This effect is displayed in Figure 2 for VCC and cal) is generated on the SCLOUT pin by the LTC4309 in an VCC2 = 5.5V and a 10k pull-up resistor on each side (50pF attempt to free the stuck low bus. Once the clock pulses on one side and 150pF on the other). Since the output side have completed, a stop bit is generated on the SCLOUT has less capacitance than the input, it rises faster and the and SDAOUT pins to reset all devices on the bus. effective propagation delay is negative. If the stuck low SDAOUT or SCLOUT recovers to a logic There is a fi nite propagation delay through the connec- high, the FAULT flag clears, and the LTC4309 waits for tion circuitry for falling waveforms. Figure 3 shows the either a stop bit or a bus idle condition to activate the falling edge waveforms for the same pull-up resistors and connection circuitry to reconnect the input and output equivalent capacitance conditions as used in Figure 2. An busses. external N-channel MOSFET device pulls down the voltage If DISCEN is connected to GND, the FAULT pin will pull on the side with 150pF capacitance; LTC4309 pulls down low, but the connection circuitry will not be disabled, the voltage on the opposite side, with a delay of 85ns. This leaving the input and output busses connected. Also, no delay is always positive and is a function of supply voltage, clock or stop bit is generated. temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. When powering up into a bus stuck low condition, the connection circuitry connecting the SDA and SCL busses The Typical Performance Characteristics section shows on the I/O card with those on the backplane is not activated. Propagation Delay as a function of temperature and voltage 30ms after UVLO, the FAULT pin pulls low indicating a bus for 2.7k pull-up resistors and 50pF equivalent capacitance stuck low condition and automatic clocking and stop bit on both sides of the part. Also, the Propagation Delay as generation takes place as described above. a function of Output Capacitance curve shows that larger output capacitances translate to longer delays. Users must
READY Digital Output
quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust This pin provides a digital fl ag which is low when either setup and hold times accordingly. ENABLE is low, the start-up sequence described earlier in this section has not been completed, or the LTC4309 4309fa 9
OPERATION
OUTPUT SIDE INPUT SIDE INPUT SIDE OUTPUT SIDE 50pF 150pF 150pF 50pF 1V/DIV 1V/DIV 1V/DIV 1V/DIV 200ns/DIV 4307 F01 200ns/DIV 4307 F02
Figure 2. Input-Output Rising Edge Waveforms Figure 3. Input-Output Falling Edge Waveforms
typically 60mV. This offset is nearly independent of pull-up
Bus Stuck Low Timeout
current. (See Typical Performance curves.) When SDAOUT or SCLOUT is low, an internal timer is started. The timer is only reset by the respective pin
Propagation Delays
going high. If the bus stuck low does not go high within During a rising edge, the rise time on each side is de- 30ms (typical), the FAULT pin pulls low indicating a bus termined by the bus pull-up resistor and the equivalent stuck low condition. If DISCEN is connected to VCC, the capacitance on the line. If the pull-up resistors are the connection circuitry is disabled, breaking the connection same, a difference in rise time occurs which is directly between the respective input and output pins. In addition, proportional to the difference in capacitance between the after at least 40μs, up to 16 clock pulses at 8.5kHz (typi- two sides. This effect is displayed in Figure 2 for VCC and cal) is generated on the SCLOUT pin by the LTC4309 in an VCC2 = 5.5V and a 10k pull-up resistor on each side (50pF attempt to free the stuck low bus. Once the clock pulses on one side and 150pF on the other). Since the output side have completed, a stop bit is generated on the SCLOUT has less capacitance than the input, it rises faster and the and SDAOUT pins to reset all devices on the bus. effective propagation delay is negative. If the stuck low SDAOUT or SCLOUT recovers to a logic There is a fi nite propagation delay through the connec- high, the FAULT flag clears, and the LTC4309 waits for tion circuitry for falling waveforms. Figure 3 shows the either a stop bit or a bus idle condition to activate the falling edge waveforms for the same pull-up resistors and connection circuitry to reconnect the input and output equivalent capacitance conditions as used in Figure 2. An busses. external N-channel MOSFET device pulls down the voltage If DISCEN is connected to GND, the FAULT pin will pull on the side with 150pF capacitance; LTC4309 pulls down low, but the connection circuitry will not be disabled, the voltage on the opposite side, with a delay of 85ns. This leaving the input and output busses connected. Also, no delay is always positive and is a function of supply voltage, clock or stop bit is generated. temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. When powering up into a bus stuck low condition, the connection circuitry connecting the SDA and SCL busses The Typical Performance Characteristics section shows on the I/O card with those on the backplane is not activated. Propagation Delay as a function of temperature and voltage 30ms after UVLO, the FAULT pin pulls low indicating a bus for 2.7k pull-up resistors and 50pF equivalent capacitance stuck low condition and automatic clocking and stop bit on both sides of the part. Also, the Propagation Delay as generation takes place as described above. a function of Output Capacitance curve shows that larger output capacitances translate to longer delays. Users must
READY Digital Output
quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust This pin provides a digital fl ag which is low when either setup and hold times accordingly. ENABLE is low, the start-up sequence described earlier in this section has not been completed, or the LTC4309 4309fa 9