Datasheet LTC4301L (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | Hot Swappable 2-Wire Bus Buffer with Low Voltage Level Translation |
| Seiten / Seite | 12 / 7 — OPERATIO. Ready Digital Output. Connection Sense. Figure 2. Input-Output … |
| Dateiformat / Größe | PDF / 189 Kb |
| Dokumentensprache | Englisch |
OPERATIO. Ready Digital Output. Connection Sense. Figure 2. Input-Output Connection. High to Low Propagation Delay
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LTC4301L
U OPERATIO
This delay is always positive and is a function of supply tion times for a rising edge versus a falling edge in their voltage, temperature and the pull-up resistors and equiva- systems and adjust setup and hold times accordingly. lent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows the high to
Ready Digital Output
low propagation delay as a function of temperature and This pin provides a digital flag which is low when either CS voltage for 10k pull-up resistors pulled-up to VCC and is high or the start-up sequence described earlier in this 100pF equivalent capacitance on both sides of the part. section has not been completed. READY goes high when Larger output capacitances translate to longer delays (up CS is low and start-up is complete. The pin is driven by an to 150ns). Users must quantify the difference in propaga- open-drain pull-down capable of sinking 3mA while hold- ing 0.4V on the pin. Connect a resistor of 10k to VCC to provide the pull-up.
Connection Sense
INPUT OUTPUT When the CS pin is driven above 1.4V with respect to the SIDE SIDE 55pF 20pF LTC4301L’s ground, the backplane side is disconnected from the card side and the READY pin is internally pulled low. When the pin voltage is low, the part waits for data transactions on both the backplane and card sides to be 0.5V/DIV complete (as described in the Start-Up section) before 4301 F02 20ns/DIV reconnecting the two sides. At this time the internal
Figure 2. Input-Output Connection
pulldown on READY releases.
High to Low Propagation Delay U U W U APPLICATIO S I FOR ATIO Live Insertion and Capacitance Buffering Application
In most applications the LTC4301L will be used with a staggered connector where V Figure 3 illustrates applications of the LTC4301L with CC and GND will be long pins. SDA and SCL are medium length pins to ensure that the different bus pull-up and VCC voltages, demonstrating its V ability to recognize and buffer bus data levels that are CC and GND pins make contact first. This will allow the precharge circuitry to be activated on SDA and SCL before above or below its VCC supply. All of these applications they make contact. CS is a short pin that is pulled up when take advantage of the LTC4301L’s Hot SwapTM controlling, not connected. This is to ensure that the connection capacitance buffering and precharge features. If the I/O between the backplane and the cards data and clock cards were plugged directly into the backplane without the busses is not enabled until the transients associated with LTC4301L buffer, all of the backplane and card capaci- live insertion have settled. tances would add directly together, making rise- and fall- time requirements difficult to meet. Placing an LTC4301L Figure 4 shows the LTC4301L in an application where all on the edge of each card, however, isolates the card of the pins have the same length. In this case, an RC filter capacitance from the backplane. For a given I/O card, the circuit on the I/O card with a product of 10ms provides a LTC4301L drives the capacitance of everything on the card filter to prevent the LTC4301L from becoming activated and the backplane must drive only the capacitance of the until the transients associated with live insertion have LTC4301L, which is less than 10pF. settled. Connect the capacitor between VCC and CS, and the resistor from CS to GND. Hot Swap is a trademark of Linear Technology Corporation. 4301lfa 7
U OPERATIO
This delay is always positive and is a function of supply tion times for a rising edge versus a falling edge in their voltage, temperature and the pull-up resistors and equiva- systems and adjust setup and hold times accordingly. lent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows the high to
Ready Digital Output
low propagation delay as a function of temperature and This pin provides a digital flag which is low when either CS voltage for 10k pull-up resistors pulled-up to VCC and is high or the start-up sequence described earlier in this 100pF equivalent capacitance on both sides of the part. section has not been completed. READY goes high when Larger output capacitances translate to longer delays (up CS is low and start-up is complete. The pin is driven by an to 150ns). Users must quantify the difference in propaga- open-drain pull-down capable of sinking 3mA while hold- ing 0.4V on the pin. Connect a resistor of 10k to VCC to provide the pull-up.
Connection Sense
INPUT OUTPUT When the CS pin is driven above 1.4V with respect to the SIDE SIDE 55pF 20pF LTC4301L’s ground, the backplane side is disconnected from the card side and the READY pin is internally pulled low. When the pin voltage is low, the part waits for data transactions on both the backplane and card sides to be 0.5V/DIV complete (as described in the Start-Up section) before 4301 F02 20ns/DIV reconnecting the two sides. At this time the internal
Figure 2. Input-Output Connection
pulldown on READY releases.
High to Low Propagation Delay U U W U APPLICATIO S I FOR ATIO Live Insertion and Capacitance Buffering Application
In most applications the LTC4301L will be used with a staggered connector where V Figure 3 illustrates applications of the LTC4301L with CC and GND will be long pins. SDA and SCL are medium length pins to ensure that the different bus pull-up and VCC voltages, demonstrating its V ability to recognize and buffer bus data levels that are CC and GND pins make contact first. This will allow the precharge circuitry to be activated on SDA and SCL before above or below its VCC supply. All of these applications they make contact. CS is a short pin that is pulled up when take advantage of the LTC4301L’s Hot SwapTM controlling, not connected. This is to ensure that the connection capacitance buffering and precharge features. If the I/O between the backplane and the cards data and clock cards were plugged directly into the backplane without the busses is not enabled until the transients associated with LTC4301L buffer, all of the backplane and card capaci- live insertion have settled. tances would add directly together, making rise- and fall- time requirements difficult to meet. Placing an LTC4301L Figure 4 shows the LTC4301L in an application where all on the edge of each card, however, isolates the card of the pins have the same length. In this case, an RC filter capacitance from the backplane. For a given I/O card, the circuit on the I/O card with a product of 10ms provides a LTC4301L drives the capacitance of everything on the card filter to prevent the LTC4301L from becoming activated and the backplane must drive only the capacitance of the until the transients associated with live insertion have LTC4301L, which is less than 10pF. settled. Connect the capacitor between VCC and CS, and the resistor from CS to GND. Hot Swap is a trademark of Linear Technology Corporation. 4301lfa 7