Datasheet Summary SAM D21EL, SAM D21GL (Microchip) - 7

32-bit ARM-Based Microcontrollers 3. Ordering Information
SAMD 21 E 15 L - M F T Product Family Package Carrier SAMD = General Purpose Microcontroller No character = Tray (Default) T = Tape and Reel Product Series 21 = Cortex M0 + CPU, Basic Feature Set + DMA + Analog/PWM Optimized Package Grade Pin Count U = -40 - 85OC Matte Sn Plating N = -40 - 105oC Matte Sn Plating E = 32 Pins F = -40 - 125 G = 48 Pins OC Matte Sn Plating Flash Memory Density Package Type 16 = 64KB A = TQFP 15 = 32KB M = QFN Device Variant A = Default Variant L = Pinout optimized for analog and PWM
3.1 SAM D21ExL Ordering Code FLASH (bytes) SRAM (bytes) Temperature Range Package Carrier Type
ATSAMD21E15L-MNT 32K 4K 105°C QFN32 Tape & Reel ATSAMD21E15L-MFT 32K 4K 125°C QFN32 Tape & Reel ATSAMD21E15L-AFT 32K 4K 125°C TQFP32 Tape & Reel ATSAMD21E16L-MNT 64K 8K 105°C QFN32 Tape & Reel ATSAMD21E16L-MFT 64K 8K 125°C QFN32 Tape & Reel ATSAMD21E16L-AFT 64K 8K 125°C TQFP32 Tape & Reel
3.2 SAM D21GxL Ordering Code FLASH (bytes) SRAM (bytes) Temperature Range Package Carrier Type
ATSAMD21G16L-MUT 64K 8K 85°C QFN48 Tape & Reel ATSAMD21G16L-MNT 64K 8K 105°C QFN48 Tape & Reel
3.3 Device Identification
The DSU - Device Service Unit peripheral provides the Device Selection bits in the Device Identification register (DID.DEVSEL) in order to identify the device by software. The SAM D21L variants have a reset value of DID=0x1001drxx, with the LSB identifying the die number ('d'), the die revision ('r') and the device selection ('xx'). © 2017 Microchip Technology Inc.
Datasheet Summary
40001885A-page 7 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 3.1. SAM D21ExL 3.2. SAM D21GxL 3.3. Device Identification 4. Block Diagram 5. Pinout 5.1. SAM D21GxL 5.1.1. QFN48 5.2. SAM D21ExL 5.2.1. QFN32 / TQFP32 6. Product Mapping 7. Processor And Architecture 7.1. Cortex M0+ Processor 7.1.1. Cortex M0+ Configuration 7.1.2. Cortex-M0+ Peripherals 7.1.3. Cortex-M0+ Address Map 7.1.4. I/O Interface 7.1.4.1. Overview 7.1.4.2. Description 7.2. Nested Vector Interrupt Controller 7.2.1. Overview 7.2.2. Interrupt Line Mapping 7.3. Micro Trace Buffer 7.3.1. Features 7.3.2. Overview 7.4. High-Speed Bus System 7.4.1. Features 7.4.2. Configuration 7.4.3. SRAM Quality of Service 7.5. AHB-APB Bridge 7.6. PAC - Peripheral Access Controller 7.6.1. Overview 7.6.2. Register Description 7.6.2.1. PAC0 Register Description 7.6.2.1.1. Write Protect Clear 7.6.2.1.2. Write Protect Set 7.6.2.2. PAC1 Register Description 7.6.2.2.1. Write Protect Clear 7.6.2.2.2. Write Protect Set 7.6.2.3. PAC2 Register Description 7.6.2.3.1. Write Protect Clear 7.6.2.3.2. Write Protect Set 8. Packaging Information 8.1. Thermal Considerations 8.1.1. Thermal Resistance Data 8.1.2. Junction Temperature 8.2. Package Drawings 8.2.1. 48 pin QFN 8.2.2. 32 pin TQFP 8.2.3. 32 pin QFN 8.3. Soldering Profile The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service