Datasheet Summary SAM D21EL, SAM D21GL (Microchip) - 10

HerstellerMicrochip
Beschreibung32-bit ARM-Based Microcontrollers
Seiten / Seite38 / 10 — 32-bit ARM-Based Microcontrollers. Pinout. 5.1. SAM D21GxL. 5.1.1. QFN48. …
Revision02-01-2017
Dateiformat / GrößePDF / 851 Kb
DokumentenspracheEnglisch

32-bit ARM-Based Microcontrollers. Pinout. 5.1. SAM D21GxL. 5.1.1. QFN48. Datasheet Summary

32-bit ARM-Based Microcontrollers Pinout 5.1 SAM D21GxL 5.1.1 QFN48 Datasheet Summary

Modelllinie für dieses Datenblatt

ATSAMD21E15
ATSAMD21E15L
ATSAMD21E16
ATSAMD21E16L
ATSAMD21E17
ATSAMD21E18
ATSAMD21G15
ATSAMD21G16
ATSAMD21G16L
ATSAMD21G17
ATSAMD21G18
ATSAMD21J15
ATSAMD21J16
ATSAMD21J17
ATSAMD21J18

Textversion des Dokuments

32-bit ARM-Based Microcontrollers 5. Pinout 5.1 SAM D21GxL 5.1.1 QFN48
A31 A30 A28 A27 PB03 PB02 PB01 PB00 P P VDDIN VDDCORE GND P RESETN P 48 47 46 45 44 43 42 41 40 39 38 37 PA02 1 36 VDDIO PA03 2 35 GND PB04 3 34 PA25 PB05 4 33 PA24 GNDANA 5 32 PA23 VDDANA 6 31 PA22 30 PA21 PB08 7 PB09 8 29 PA20 PA04 9 28 PA19 PA05 10 27 PA18 PA06 11 26 PA17 PA07 12 25 PA16 13 14 15 16 17 18 19 20 21 22 23 24 1 1 A08 A09 A10 A1 A12 A13 A14 A15 P P P P GND PB10 PB1 P P P P VDDIO DIGITAL PIN ANALOG PIN OSCILLATOR GROUND INPUT SUPPLY REGULATED OUTPUT SUPPLY RESET PIN © 2017 Microchip Technology Inc.
Datasheet Summary
40001885A-page 10 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 3.1. SAM D21ExL 3.2. SAM D21GxL 3.3. Device Identification 4. Block Diagram 5. Pinout 5.1. SAM D21GxL 5.1.1. QFN48 5.2. SAM D21ExL 5.2.1. QFN32 / TQFP32 6. Product Mapping 7. Processor And Architecture 7.1. Cortex M0+ Processor 7.1.1. Cortex M0+ Configuration 7.1.2. Cortex-M0+ Peripherals 7.1.3. Cortex-M0+ Address Map 7.1.4. I/O Interface 7.1.4.1. Overview 7.1.4.2. Description 7.2. Nested Vector Interrupt Controller 7.2.1. Overview 7.2.2. Interrupt Line Mapping 7.3. Micro Trace Buffer 7.3.1. Features 7.3.2. Overview 7.4. High-Speed Bus System 7.4.1. Features 7.4.2. Configuration 7.4.3. SRAM Quality of Service 7.5. AHB-APB Bridge 7.6. PAC - Peripheral Access Controller 7.6.1. Overview 7.6.2. Register Description 7.6.2.1. PAC0 Register Description 7.6.2.1.1. Write Protect Clear 7.6.2.1.2. Write Protect Set 7.6.2.2. PAC1 Register Description 7.6.2.2.1. Write Protect Clear 7.6.2.2.2. Write Protect Set 7.6.2.3. PAC2 Register Description 7.6.2.3.1. Write Protect Clear 7.6.2.3.2. Write Protect Set 8. Packaging Information 8.1. Thermal Considerations 8.1.1. Thermal Resistance Data 8.1.2. Junction Temperature 8.2. Package Drawings 8.2.1. 48 pin QFN 8.2.2. 32 pin TQFP 8.2.3. 32 pin QFN 8.3. Soldering Profile The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service