Datasheet MCP606, MCP607, MCP608 (Microchip)

MCP606/7/8/9 2.5V to 6.0V Micropower CMOS Op Amp Features Description
• Low Input Offset Voltage: 250 µV (maximum) The MCP606/7/8/9 family of operational amplifiers (op amps) from Microchip Technology Inc. are unity-gain • Rail-to-Rail Output stable with low offset voltage (250 µV, maximum). • Low Input Bias Current: 80 pA (maximum at Performance characteristics include rail-to-rail output +85°C) swing capability and low input bias current (80 pA at • Low Quiescent Current: 25 µA (maximum) +85°C, maximum). These features make this family of • Power Supply Voltage: 2.5V to 6.0V op amps well suited for single-supply, precision, • Unity-Gain Stable high-impedance, battery-powered applications. • Chip Select (CS) Capability:
MCP608
The single is available in standard 8-lead PDIP, SOIC • Industrial Temperature Range: -40°C to +85°C and TSSOP packages, as well as in a SOT-23-5 • No Phase Reversal package. The single MCP608 with Chip Select (CS) is offered in the standard 8-lead PDIP, SOIC and TSSOP • Available in Single, Dual and Quad Packages packages. The dual MCP607 is offered in the standard 8-lead PDIP, SOIC and TSSOP packages. Finally, the
Typical Applications
quad MCP609 is offered in the standard 14-lead PDIP, • Battery Power Instruments SOIC and TSSOP packages. All devices are fully specified from -40°C to +85°C, with power supplies • High-Impedance Applications from 2.5V to 6.0V. • Strain Gauges • Medical Instruments
Package Types
• Test Equipment
MCP606 MCP606 Design Aids
PDIP, SOIC,TSSOP SOT-23-5 NC 1 8 NC V 1 5 V OUT DD • SPICE Macro Models V 2 7 V V 2 • FilterLab® Software IN– DD SS VIN+ 3 6 VOUT VIN+ 3 4 VIN– • Mindi™ Circuit Designer & Simulator VSS 4 5 NC • Analog Demonstration and Evaluation Boards • Application Notes
MCP607 MCP608
PDIP, SOIC,TSSOP PDIP, SOIC,TSSOP
Typical Application
V 1 8 V OUTA DD NC 1 8 CS V = V + ( ⁄ R ) V 2 7 V V 2 7 V OUT LM I R R L INA– OUTB IN– DD SEN F G IL VINA+ 3 6 VINB– VIN+ 3 6 VOUT VSS 4 5 VINB+ VSS 4 5 NC R R G F To Load 5 kΩ 50 kΩ (VLP)
MCP609
2.5V PDIP, SOIC,TSSOP to VOUT V 1 14 V OUTA 6.0V OUTD
MCP606
V 2 13 INA– VIND– RSEN To Load VINA+ 3 12 VIND+ 10Ω (VLM) VDD 4 11 VSS V 5 10 INB+ VINC+ 6 9
Low-Side Battery Current Sensor
VINB– VINC– VOUTB 7 8 VOUTC © 2009 Microchip Technology Inc. DS11177F-page 1 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP608. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage at VDD = 5.5V. FIGURE 2-2: Input Offset Voltage at VDD = 2.5V. FIGURE 2-3: Quiescent Current vs. Power Supply Voltage. FIGURE 2-4: Input Offset Voltage Drift Magnitude at VDD = 5.5V. FIGURE 2-5: Input Offset Voltage Drift Magnitude at VDD = 2.5V. FIGURE 2-6: Quiescent Current vs. Ambient Temperature. FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature. FIGURE 2-8: Open-Loop Gain and Phase vs. Frequency. FIGURE 2-9: Channel-to-Channel Separation (MCP607 and MCP609 only). FIGURE 2-10: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-11: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-14: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-15: CMRR, PSRR vs. Frequency. FIGURE 2-16: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-19: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-20: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-21: Slew Rate vs. Ambient Temperature. FIGURE 2-22: Output Voltage Headroom vs. Ambient Temperature at RL = 5 kW. FIGURE 2-23: The MCP606/7/8/9 Show No Phase Reversal. FIGURE 2-24: Output Short Circuit Current Magnitude vs. Ambient Temperature. FIGURE 2-25: Large-signal, Non-inverting Pulse Response. FIGURE 2-26: Small-signal, Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) Hysteresis (MCP608 only). FIGURE 2-28: Large-signal, Inverting Pulse Response. FIGURE 2-29: Small-signal, Inverting Pulse Response. FIGURE 2-30: Amplifier Output Response Times vs. Chip Select (CS) Pulse (MCP608 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 MCP608 Chip Select 4.5 Supply Bypass 4.6 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.7 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.8 Application Circuits FIGURE 4-8: Low Side Battery Current Sensor. FIGURE 4-9: Photodiode (in Photo-voltaic mode) and Transimpedance Amplifier. FIGURE 4-10: Photodiode (in Photo- conductive mode) and Transimpedance Amplifier. FIGURE 4-11: Two Op Amp Instrumentation Amplifier. FIGURE 4-12: Three Op Amp Instrumentation Amplifier. FIGURE 4-13: Precision Gain with Good Load Isolation. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information