Datasheet AD8253 (Analog Devices) - 10

Data Sheet AD8253 20 V) 18 µ E ( 16 G A T L 14 VO 12 SET F F 10 O T 8 PU N I 6 N E I G 4 N A
12 0
H 2
3-
500nV/DIV 1s/DIV C
98 06
0 0.01 0.1 1 10
1503-
WARM-UP TIME (Minutes)
98 06 Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1000 Figure 15. Change in Input Offset Voltage vs. Warm-Up Time, G = 1000
18 140 16 120 14 G = 1000 100 G = 100 ) 12 √Hz B) 80 A/ 10 d p ( G = 1 ( E RR IS 8 S 60 P G = 10 NO 6 40 4 20 2 0 0
13
1 10 100 1k 10k 100k
16 0
10 100 1k 10k 100k 1M
0 3- 3- 98
FREQUENCY (Hz) FREQUENCY (Hz)
698 06 0 Figure 13. Current Noise Spectral Density vs. Frequency Figure 16. Positive PSRR vs. Frequency, RTI
140 120 G = 100 G = 1000 100 B) 80 d ( RR G = 10 S 60 P 40 G = 1
4
20
01 3-
140pA/DIV 1s/DIV
98 06
010 100 1k 10k 100k 1M
17 0 3-
FREQUENCY (Hz)
698 0 Figure 14. 0.1 Hz to 10 Hz Current Noise Figure 17. Negative PSRR vs. Frequency, RTI Rev. B | Page 9 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ANALOG-TO-DIGITAL CONVERTER APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE