Datasheet AD8253 (Analog Devices) - 9

AD8253 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
TA @ 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted.
210 240 180 210 S 150 S T 180 T UNI UNI F 120 150 F R O R O 120 BE 90 BE M M NU 90 NU 60 60 30 30 0 0
6
–60 –40 –20 0 20
09 00
–60 –40 –20 0 20 40 60
0 3- 3-
CMRR (µV/V)
98
INPUT OFFSET CURRENT (nA)
98 06 06 Figure 6. Typical Distribution of CMRR, G = 1 Figure 9. Typical Distribution of Input Offset Current
90 180 80 150 70 S T 120 ) 60 UNI F √Hz V/ 50 n R O 90 G = 1 BE G = 100 ISE ( 40 O NUM N 60 30 G = 10 20 30 10 0 G = 1000 –200 –100 0 100 200
07
0
0 10 3-
1 10 100 1k 10k 100k
0
INPUT OFFSET VOLTAGE, V
98 3-
OSI , RTI (µV)
06 698
FREQUENCY (Hz)
0 Figure 7. Typical Distribution of Offset Voltage, VOSI Figure 10. Voltage Spectral Density Noise vs. Frequency
300 250 S T UNI 200 F R O 150 BE M NU 100 50
11 0 3-
2µV/DIV 1s/DIV
98
0
06 8
–90 –60 –30 0 30 60 90
00 3-
INPUT BIAS CURRENT (nA)
98 06 Figure 8. Typical Distribution of Input Bias Current Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Rev. B | Page 8 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ANALOG-TO-DIGITAL CONVERTER APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE