Datasheet AD5382 (Analog Devices) - 9

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AD5382 Data Sheet Parameter AD5382-31 Unit Test Conditions/Comments
LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage 0.4 V max Sinking 200 μA VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 μA High Impedance Leakage Current ±1 μA max SDO only High Impedance Output Capacitance 5 pF typ SDO only LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Three-State Leakage Current ±1 μA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 2.7/3.6 V min/max DVDD 2.7/5.5 V min/max Power Supply Sensitivity3 ∆Midscale/∆ΑVDD –85 dB typ AIDD 0.375 mA/channel max Outputs unloaded; boost off; 0.25 mA/channel typ 0.475 mA/channel max Outputs unloaded; boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD VIL = DGND AIDD (Power-Down) 20 μA max Typically 100 nA DIDD (Power-Down) 20 μA max Typically 1 μA Power Dissipation 39 mW max Outputs unloaded; boost off; AVDD = DVDD = 3 V 1 AD5382-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C. 2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded accuracy specifications.
AC CHARACTERISTICS1
AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND= 0 V.
Table 3. Parameter All Unit Test Conditions/Comments
DYNAMIC PERFORMANCE Output Voltage Settling Time2 1/4 scale to 3/4 scale change settling to ±1 LSB 3 μs typ 8 μs max Slew Rate2 1.5 V/μs typ Boost mode off, CR11 = 0 2.5 V/μs typ Boost mode on, CR11 = 1 Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ DAC-to-DAC Crosstalk 1 nV-s typ See the Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test Output Noise 0.1 Hz to 10 Hz 15 μV p-p typ External reference, midscale loaded to DAC 40 μV p-p typ Internal reference, midscale loaded to DAC Output Noise Spectral Density At 1 kHz 150 nV/√Hz typ At 10 kHz 100 nV/√Hz typ 1 Guaranteed by design and characterization, not production tested. 2 The slew rate can be programmed via the current boost control bit (CR11) in the AD5382 control register. Rev. D | Page 8 of 40 Document Outline Features Integrated Functions Applications Functional Block Diagram Table of Contents Revision History General Description Specifications AD5382-5 Specifications AD5382-3 Specifications AC Characteristics Timing Characteristics SPI-, QSPI-, MICROWIRE-, or DSP-Compatible Serial Interface I2C Serial Interface Parallel Interface Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write Clear Code Soft Clear Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down AD5382 Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer Start and Stop Conditions Repeated Start Conditions Acknowledge Bit (ACK) AD5382 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pins A4 to A0 Pins DB13 to DB0 Microprocessor Interfacing Parallel Interface AD5382 to MC68HC11 AD5382 to PIC16C6x/7x AD5382 to 8051 AD5382 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Monitor Function Toggle Mode Function Thermal Monitor Function AD5382 in a MEMS-Based Optical Switch Optical Attenuators Outline Dimensions Ordering Guide