Datasheet AD5382 (Analog Devices) - 2

HerstellerAnalog Devices
Beschreibung32-Channel, 3 V/5 V, Single-Supply, 14-Bit denseDAC
Seiten / Seite41 / 2 — AD5382* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017. …
RevisionD
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DokumentenspracheEnglisch

AD5382* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017. COMPARABLE PARTS. REFERENCE MATERIALS

AD5382* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS

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AD5382* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS
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Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
EVALUATION KITS Technical Articles
• AD5382 Evaluation Board • Software Calibration Reduces D/A Converter Offset and Gain Errors
DOCUMENTATION Application Notes DESIGN RESOURCES
• AN-1225: 32 Channels of Programmable Voltage with • AD5382 Material Declaration Excellent Temperature Drift Performance Using the • PCN-PDN Information AD5382 DAC • Quality And Reliability • AN-1226: AD5382 Channel Monitor Function • Symbols and Footprints
Data Sheet
• AD5382: 32-Channel, 3 V/5 V, Single-Supply, 14-Bit
DISCUSSIONS
denseDAC Data Sheet View all AD5382 EngineerZone Discussions.
Product Highlight
• Extending the denseDAC™ Multichannel D/As
SAMPLE AND BUY User Guides
Visit the product page to see pricing options. • UG-757: Evaluating the AD5380/AD5382 40-/32-Channel, 14-Bit Voltage Output DACs with On-Chip Reference
TECHNICAL SUPPORT SOFTWARE AND SYSTEMS REQUIREMENTS
Submit a technical question or find your regional support number. • AD5380 IIO Multi-Channel DAC Linux Driver
DOCUMENT FEEDBACK
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Document Outline Features Integrated Functions Applications Functional Block Diagram Table of Contents Revision History General Description Specifications AD5382-5 Specifications AD5382-3 Specifications AC Characteristics Timing Characteristics SPI-, QSPI-, MICROWIRE-, or DSP-Compatible Serial Interface I2C Serial Interface Parallel Interface Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write Clear Code Soft Clear Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down AD5382 Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer Start and Stop Conditions Repeated Start Conditions Acknowledge Bit (ACK) AD5382 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pins A4 to A0 Pins DB13 to DB0 Microprocessor Interfacing Parallel Interface AD5382 to MC68HC11 AD5382 to PIC16C6x/7x AD5382 to 8051 AD5382 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Monitor Function Toggle Mode Function Thermal Monitor Function AD5382 in a MEMS-Based Optical Switch Optical Attenuators Outline Dimensions Ordering Guide