Datasheet AD9142 (Analog Devices) - 7

AD9142 Data Sheet DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
CMOS INPUT LOGIC LEVEL Input Logic High DVDD18 = 1.8 V 1.2 V Logic Low DVDD18 = 1.8 V 0.6 V CMOS OUTPUT LOGIC LEVEL Output Logic High DVDD18 = 1.8 V 1.4 V Logic Low DVDD18 = 1.8 V 0.4 V LVDS RECEIVER INPUTS Input Voltage Range VIA or VIB 825 1675 mV Input Differential Threshold VIDTH Data and FRAME inputs −100 +100 mV DCI input −225 +225 mV Input Differential Hysteresis VIDTHH to VIDTHL 20 mV Receiver Differential Input Impedance RIN 120 Ω DAC UPDATE RATE 1600 MSPS DAC Adjusted Update Rate 2× interpolation 250 MSPS DAC CLOCK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage Self biased input, ac-coupled 1.25 V REFCLK/SYNCCLK INPUT (REFP/SYNCP, REFN/SYNCN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage 1.25 V Input Clock Frequency 1 GHz ≤ fVCO ≤ 2.1 GHz 450 MHz SERIAL PORT INTERFACE Maximum Clock Rate SCLK 40 MHz Minimum Pulse Width High tPWH 12.5 ns Low tPWL 12.5 ns Setup Time tDS SDIO to SCLK 1.5 ns Hold Time tDH SDIO to SCLK 0.68 ns Setup Time tDCSB CS to SCLK 2.38 1.4 ns Rev. 0 | Page 6 of 64 Document Outline Features Applications General Description Product Highlights Revision History Functional Block Diagram Specifications DC Specifications Digital Specifications DAC Latency Specifications Latency Variation Specifications0F AC Specifications Operating Speed Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Serial Port Operation Data Format Serial Port Pin Descriptions Serial Port Options Data Interface LVDS Input Data Ports Word Interface Mode Byte Interface Mode Data Interface Configuration Options LVDS Input Level Requirements Interface Delay Line Interface Timing Requirements SPI Sequence to Enable Delay Line-Based Mode FIFO Operation Resetting the FIFO Serial Port Initiated FIFO Reset Frame Initiated FIFO Reset Monitoring the FIFO Status Digital Datapath Interpolation Filters 2× Interpolation Mode 4× Interpolation Mode 8× Interpolation Mode Digital Modulation fS/4 Modulation NCO Modulation Updating the Frequency Tuning Word SPI Initiated Update Frame Initiated Update Datapath Configuration Digital Quadrature Gain and Phase Adjustment Quadrature Gain Adjustment Quadrature Phase Adjustment DC Offset Adjustment Inverse Sinc Filter Input Signal Power Detection and Protection Transmit Enable Function Digital Function Configuration Multidevice Synchronization and Fixed Latency Very Small Inherent Latency Variation Further Reducing the Latency Variation Set Up and Hold Timing Requirement Synchronization Implementation Synchronization Procedures Synchronization Procedure for PLL Off Synchronization Procedure for PLL On Interrupt Request Operation Interrupt Working Mechanism Interrupt Service Routine Temperature Sensor DAC Input Clock Configurations Driving the DACCLK and REFCLK Inputs Direct Clocking Clock Multiplication PLL Settings Configuring the VCO Tuning Band Automatic VCO Band Select Manual VCO Band Select Automatic Mode Sequence Manual Mode Analog Outputs Transmit DAC Operation Transmit DAC Transfer Function Transmit DAC Output Configurations Interfacing to Modulators Baseband Filter Implementation Reducing LO Leakage and Unwanted Sidebands Example Start-Up Routine Device Configuration and Start-Up Sequence Derived PLL Settings Derived NCO Settings Start-Up Sequence Device Configuration Register Map and Description SPI Configure Register Power-Down Control Register Interrupt Enable0 Register Interrupt Enable1 Register Interrupt Flag0 Register Interrupt Flag1 Register Interrupt Select0 Register Interrupt Select1 Register DAC Clock Receiver Control Register Ref Clock Receiver Control Register PLL Control Register PLL Control Register PLL Control Register PLL Status Register PLL Status Register IDAC FS Adjust LSB Register IDAC FS Adjust MSB Register QDAC FS Adjust LSB Register QDAC FS Adjust MSB Register Die Temperature Sensor Control Register Die Temperature LSB Register Die Temperature MSB Register Chip ID Register Interrupt Configuation Register Sync CTRL Register Frame Reset CTRL Register FIFO Level Configuration Register FIFO Level Readback Register FIFO CTRL Register Data Format Select Register Datapath Control Register Interpolation Control Register Over Threshold CTRL0 Register Over Threshold CTRL1 Register Over Threshold CTRL2 Register Input Power Readback LSB Register Input Power Readback MSB Register NCO Control Register NCO_FREQ_TUNING_WORD0 Register NCO_FREQ_TUNING_WORD1 Register NCO_FREQ_TUNING_WORD2 Register NCO_FREQ_TUNING_WORD3 Register NCO_PHASE_OFFSET0 Register NCO_PHASE_OFFSET1 Register IQ_PHASE_ADJ0 Register IQ_PHASE_ADJ1 Register IDAC_DC_OFFSET0 Register IDAC_DC_OFFSET1 Register QDAC_DC_OFFSET0 Register QDAC_DC_OFFSET1 Register IDAC_GAIN_ADJ Register QDAC_GAIN_ADJ Register Gain Step Control0 Register Gain Step Control1 Register TX Enable Control Register DAC Output Control Register Data Receiver Test Control Register Data Receiver Test Control Register Device Configuration0 Register Version Register Device Configuration1 Register Device Configuration2 Register DAC Latency and System Skews DAC Latency Variations FIFO Latency Variation Clock Generation Latency Variation Correcting System Skews Packaging and Ordering Information Outline Dimensions Ordering Guide