Datasheet AD7703 (Analog Devices) - 7

AD7703 PIN CONFIGURATION Table I. Bit Weight Table (2.5 V Reference Voltage) DIP, CERDIP, SOIC Unipolar Mode Bipolar Mode MODE 1 20 SDATA ppm ppm CLKOUT 19 SCLK 2
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V LSB % FS FS LSB % FS FS CLKIN 3 18 DRDY
0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12
SC1 4 17 SC2 AD7703
1.192 0.5 0.0000477 0.48 0.26 0.0000238 0.24
DGND 5 16 CS TOP VIEW
2.384 1.00 0.0000954 0.95 0.5 0.0000477 0.48
DV 6 (Not to Scale) 15 DV SS DD
4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95
AV AV SS 7 14 DD
9.537 4.00 0.0003814 3.81 2.00 0.0001907 1.91
AGND 8 13 CAL AIN 9 12 BP/UP VREF 10 11 SLEEP PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description
1 MODE Selects the Serial Interface Mode. If MODE is tied to DGND, the Synchronous External Clocking (SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB coming first. If MODE is tied to +5 V, the AD7703 operates in the Synchronous Self-Clocking (SSC) mode. SCLK is configured as an output, with a clock frequency for fCLKIN/4 and 25% duty cycle. 2 CLKOUT Clock Output to Generate an Internal Master Clock by Connecting a Crystal between CLKOUT and CLKIN. If an external clock is used, CLKOUT is not connected. 3 CLKIN Clock Input for External Clock. 4, 17 SC1, SC2 System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration performed. 5 DGND Digital Ground. Ground reference for all digital signals. 6 DVSS Digital Negative Supply, –5 V Nominal. 7 AVSS Analog Negative Supply, –5 V Nominal. 8 AGND Analog Ground. Ground reference for all analog signals. 9 AIN Analog Input. 10 VREF Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale in the Unipolar mode and the value of both positive and negative full scale in the Bipolar mode. 11 SLEEP Sleep Mode Pin. When this pin is taken low, the AD7703 goes into a low power mode with typically 10 µW power consumption. 12 BP/UP Bipolar/Unipolar Mode Pin. When this pin is low, the AD7703 is configured for a unipolar input range going from AGND to VREF. When Pin 12 is high, the AD7703 is configured for a bipolar input range, ±VREF. 13 CAL Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7703 is reset and performs a calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize the operation of several AD7703s. 14 AVDD Analog Positive Supply, 5 V Nominal. 15 DVDD Digital Positive Supply, 5 V Nominal. 16 CS Chip Select Input. When CS is brought low, the AD7703 will begin to transmit serial data in a format determined by the state of the MODE pin. 18 DRDY Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after trans- mission of a word is completed. It also goes high for four clock cycles when a new data-word is being loaded into the output register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not. 19 SCLK Serial Clock Input/Output. The SCLK pin is configured as an input or output, dependent on the type of serial data transmission that has been selected by the MODE pin. When configured as an output in the Synchronous Self-Clocking mode, it has a frequency of fCLKIN/4 and a duty cycle of 25%. 20 SDATA Serial Data Output. The AD7703’s output data is available at this pin as a 20-bit serial word. –6– REV. E Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span PIN CONFIGURATION DIP, CERDIP, SOIC PIN FUNCTION DESCRIPTIONS GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7703 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES ACCURACY AUTOCALIBRATION Initiating Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS POWER SUPPLIES AND GROUNDING SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS REVISION HISTORY