Datasheet AD9059 (Analog Devices) - 5

AD9059 PIN FUNCTION DESCRIPTIONS N N + 3 N + 5 Pin No. Mnemonic Function AIN N + 1
1, 28 AINA, AINB Analog Inputs for ADC A and B.
N + 2 N + 4
2 VREF Internal Voltage Reference (2.5 V
t
Typical); Bypass with 0.1 µF to
A
Ground or Overdrive with External
ENCODE tEH tEL
Voltage Reference.
t
3 PWRDN Power-Down Function Select; Logic
V
HIGH for Power-Down Mode
DIGITAL N – 3 N – 2 N – 1 N N + 1 N + 2 OUTPUTS
(Digital Outputs Go to High- Impedance State).
tPD
4, 25 VD Analog 5 V Power Supply.
MIN TYP MAX
5, 24, 27 GND Ground.
tA APERTURE DELAY 2.7ns tEH PULSEWIDTH HIGH 6.7ns 166ns
6, 23 VDD Digital Output Power Supply.
tEL PULSEWIDTH LOW 6.7ns 166ns
Nominally 3 V to 5 V.
tV OUTPUT VALID TIME 4.0ns 6.6n t OUTPUT PROP DELAY
7–14 D7A–D0A Digital Outputs of ADC A.
PD 9.5ns 14.2ns
22–15 D7B–D0B Digital Outputs of ADC B. Figure 1. Timing Diagram 26 ENCODE Encode Clock for ADCs A and B
PIN CONFIGURATION
(ADCs Sample Simultaneously on the Rising Edge of ENCODE).
AINA 1 28 AINB Table I. Digital Coding (VREF = 2.5 V) VREF 2 27 GND PWRDN 3 26 ENCODE Analog Input (V) Voltage Level Digital Output V 4 25 V D D GND 5 24 GND
3.0 Positive Full Scale 1111 1111
AD9059 V 6 23
2.502 Midscale + 1/2 LSB 1000 0000
DD TOP VIEW VDD D7A (MSB) 7 (Not to Scale) 22
2.498 Midscale – 1/2 LSB 0111 1111
D7B (MSB) D6A 8 21
2.0 Negative Full Scale 0000 0000
D6B D5A 9 20 D5B D4A 10 19 D4B D3A 11 18 D3B D2A 12 17 D2B D1A 13 16 D1B D0A (LSB) 14 15 D0B (LSB)
–4– REV. A Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics THEORY OF OPERATION USING THE AD9059 Analog Inputs Voltage Reference Digital Logic (5 V/3 V Systems) Timing Power Dissipation Applications Evaluation Board OUTLINE DIMENSIONS Revision History